1 module capstone.xcore; 2 3 extern (C): 4 5 /* Capstone Disassembly Engine */ 6 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ 7 8 /// Operand type for instruction's operands 9 enum xcore_op_type 10 { 11 XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 12 XCORE_OP_REG = 1, ///< = CS_OP_REG (Register operand). 13 XCORE_OP_IMM = 2, ///< = CS_OP_IMM (Immediate operand). 14 XCORE_OP_MEM = 3 ///< = CS_OP_MEM (Memory operand). 15 } 16 17 /// XCore registers 18 enum xcore_reg 19 { 20 XCORE_REG_INVALID = 0, 21 22 XCORE_REG_CP = 1, 23 XCORE_REG_DP = 2, 24 XCORE_REG_LR = 3, 25 XCORE_REG_SP = 4, 26 XCORE_REG_R0 = 5, 27 XCORE_REG_R1 = 6, 28 XCORE_REG_R2 = 7, 29 XCORE_REG_R3 = 8, 30 XCORE_REG_R4 = 9, 31 XCORE_REG_R5 = 10, 32 XCORE_REG_R6 = 11, 33 XCORE_REG_R7 = 12, 34 XCORE_REG_R8 = 13, 35 XCORE_REG_R9 = 14, 36 XCORE_REG_R10 = 15, 37 XCORE_REG_R11 = 16, 38 39 // pseudo registers 40 XCORE_REG_PC = 17, ///< pc 41 42 // internal thread registers 43 // see The-XMOS-XS1-Architecture(X7879A).pdf 44 XCORE_REG_SCP = 18, ///< save pc 45 XCORE_REG_SSR = 19, //< save status 46 XCORE_REG_ET = 20, //< exception type 47 XCORE_REG_ED = 21, //< exception data 48 XCORE_REG_SED = 22, //< save exception data 49 XCORE_REG_KEP = 23, //< kernel entry pointer 50 XCORE_REG_KSP = 24, //< kernel stack pointer 51 XCORE_REG_ID = 25, //< thread ID 52 53 XCORE_REG_ENDING = 26 // <-- mark the end of the list of registers 54 } 55 56 /// Instruction's operand referring to memory 57 /// This is associated with XCORE_OP_MEM operand type above 58 struct xcore_op_mem 59 { 60 ubyte base; ///< base register, can be safely interpreted as 61 ///< a value of type `xcore_reg`, but it is only 62 ///< one byte wide 63 ubyte index; ///< index register, same conditions apply here 64 int disp; ///< displacement/offset value 65 int direct; ///< +1: forward, -1: backward 66 } 67 68 /// Instruction operand 69 struct cs_xcore_op 70 { 71 xcore_op_type type; ///< operand type 72 union 73 { 74 xcore_reg reg; ///< register value for REG operand 75 int imm; ///< immediate value for IMM operand 76 xcore_op_mem mem; ///< base/disp value for MEM operand 77 } 78 } 79 80 /// Instruction structure 81 struct cs_xcore 82 { 83 /// Number of operands of this instruction, 84 /// or 0 when instruction has no operand. 85 ubyte op_count; 86 cs_xcore_op[8] operands; ///< operands for this instruction. 87 } 88 89 /// XCore instruction 90 enum xcore_insn 91 { 92 XCORE_INS_INVALID = 0, 93 94 XCORE_INS_ADD = 1, 95 XCORE_INS_ANDNOT = 2, 96 XCORE_INS_AND = 3, 97 XCORE_INS_ASHR = 4, 98 XCORE_INS_BAU = 5, 99 XCORE_INS_BITREV = 6, 100 XCORE_INS_BLA = 7, 101 XCORE_INS_BLAT = 8, 102 XCORE_INS_BL = 9, 103 XCORE_INS_BF = 10, 104 XCORE_INS_BT = 11, 105 XCORE_INS_BU = 12, 106 XCORE_INS_BRU = 13, 107 XCORE_INS_BYTEREV = 14, 108 XCORE_INS_CHKCT = 15, 109 XCORE_INS_CLRE = 16, 110 XCORE_INS_CLRPT = 17, 111 XCORE_INS_CLRSR = 18, 112 XCORE_INS_CLZ = 19, 113 XCORE_INS_CRC8 = 20, 114 XCORE_INS_CRC32 = 21, 115 XCORE_INS_DCALL = 22, 116 XCORE_INS_DENTSP = 23, 117 XCORE_INS_DGETREG = 24, 118 XCORE_INS_DIVS = 25, 119 XCORE_INS_DIVU = 26, 120 XCORE_INS_DRESTSP = 27, 121 XCORE_INS_DRET = 28, 122 XCORE_INS_ECALLF = 29, 123 XCORE_INS_ECALLT = 30, 124 XCORE_INS_EDU = 31, 125 XCORE_INS_EEF = 32, 126 XCORE_INS_EET = 33, 127 XCORE_INS_EEU = 34, 128 XCORE_INS_ENDIN = 35, 129 XCORE_INS_ENTSP = 36, 130 XCORE_INS_EQ = 37, 131 XCORE_INS_EXTDP = 38, 132 XCORE_INS_EXTSP = 39, 133 XCORE_INS_FREER = 40, 134 XCORE_INS_FREET = 41, 135 XCORE_INS_GETD = 42, 136 XCORE_INS_GET = 43, 137 XCORE_INS_GETN = 44, 138 XCORE_INS_GETR = 45, 139 XCORE_INS_GETSR = 46, 140 XCORE_INS_GETST = 47, 141 XCORE_INS_GETTS = 48, 142 XCORE_INS_INCT = 49, 143 XCORE_INS_INIT = 50, 144 XCORE_INS_INPW = 51, 145 XCORE_INS_INSHR = 52, 146 XCORE_INS_INT = 53, 147 XCORE_INS_IN = 54, 148 XCORE_INS_KCALL = 55, 149 XCORE_INS_KENTSP = 56, 150 XCORE_INS_KRESTSP = 57, 151 XCORE_INS_KRET = 58, 152 XCORE_INS_LADD = 59, 153 XCORE_INS_LD16S = 60, 154 XCORE_INS_LD8U = 61, 155 XCORE_INS_LDA16 = 62, 156 XCORE_INS_LDAP = 63, 157 XCORE_INS_LDAW = 64, 158 XCORE_INS_LDC = 65, 159 XCORE_INS_LDW = 66, 160 XCORE_INS_LDIVU = 67, 161 XCORE_INS_LMUL = 68, 162 XCORE_INS_LSS = 69, 163 XCORE_INS_LSUB = 70, 164 XCORE_INS_LSU = 71, 165 XCORE_INS_MACCS = 72, 166 XCORE_INS_MACCU = 73, 167 XCORE_INS_MJOIN = 74, 168 XCORE_INS_MKMSK = 75, 169 XCORE_INS_MSYNC = 76, 170 XCORE_INS_MUL = 77, 171 XCORE_INS_NEG = 78, 172 XCORE_INS_NOT = 79, 173 XCORE_INS_OR = 80, 174 XCORE_INS_OUTCT = 81, 175 XCORE_INS_OUTPW = 82, 176 XCORE_INS_OUTSHR = 83, 177 XCORE_INS_OUTT = 84, 178 XCORE_INS_OUT = 85, 179 XCORE_INS_PEEK = 86, 180 XCORE_INS_REMS = 87, 181 XCORE_INS_REMU = 88, 182 XCORE_INS_RETSP = 89, 183 XCORE_INS_SETCLK = 90, 184 XCORE_INS_SET = 91, 185 XCORE_INS_SETC = 92, 186 XCORE_INS_SETD = 93, 187 XCORE_INS_SETEV = 94, 188 XCORE_INS_SETN = 95, 189 XCORE_INS_SETPSC = 96, 190 XCORE_INS_SETPT = 97, 191 XCORE_INS_SETRDY = 98, 192 XCORE_INS_SETSR = 99, 193 XCORE_INS_SETTW = 100, 194 XCORE_INS_SETV = 101, 195 XCORE_INS_SEXT = 102, 196 XCORE_INS_SHL = 103, 197 XCORE_INS_SHR = 104, 198 XCORE_INS_SSYNC = 105, 199 XCORE_INS_ST16 = 106, 200 XCORE_INS_ST8 = 107, 201 XCORE_INS_STW = 108, 202 XCORE_INS_SUB = 109, 203 XCORE_INS_SYNCR = 110, 204 XCORE_INS_TESTCT = 111, 205 XCORE_INS_TESTLCL = 112, 206 XCORE_INS_TESTWCT = 113, 207 XCORE_INS_TSETMR = 114, 208 XCORE_INS_START = 115, 209 XCORE_INS_WAITEF = 116, 210 XCORE_INS_WAITET = 117, 211 XCORE_INS_WAITEU = 118, 212 XCORE_INS_XOR = 119, 213 XCORE_INS_ZEXT = 120, 214 215 XCORE_INS_ENDING = 121 // <-- mark the end of the list of instructions 216 } 217 218 /// Group of XCore instructions 219 enum xcore_insn_group 220 { 221 XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID 222 223 // Generic groups 224 // all jump instructions (conditional+direct+indirect jumps) 225 XCORE_GRP_JUMP = 1, ///< = CS_GRP_JUMP 226 227 XCORE_GRP_ENDING = 2 // <-- mark the end of the list of groups 228 }