1 /* Capstone Disassembly Engine */ 2 /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ 3 4 module capstone.tms320c64x; 5 6 extern (C): 7 8 enum tms320c64x_op_type 9 { 10 TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 11 TMS320C64X_OP_REG = 1, ///< = CS_OP_REG (Register operand). 12 TMS320C64X_OP_IMM = 2, ///< = CS_OP_IMM (Immediate operand). 13 TMS320C64X_OP_MEM = 3, ///< = CS_OP_MEM (Memory operand). 14 TMS320C64X_OP_REGPAIR = 64 ///< Register pair for double word ops 15 } 16 17 enum tms320c64x_mem_disp 18 { 19 TMS320C64X_MEM_DISP_INVALID = 0, 20 TMS320C64X_MEM_DISP_CONSTANT = 1, 21 TMS320C64X_MEM_DISP_REGISTER = 2 22 } 23 24 enum tms320c64x_mem_dir 25 { 26 TMS320C64X_MEM_DIR_INVALID = 0, 27 TMS320C64X_MEM_DIR_FW = 1, 28 TMS320C64X_MEM_DIR_BW = 2 29 } 30 31 enum tms320c64x_mem_mod 32 { 33 TMS320C64X_MEM_MOD_INVALID = 0, 34 TMS320C64X_MEM_MOD_NO = 1, 35 TMS320C64X_MEM_MOD_PRE = 2, 36 TMS320C64X_MEM_MOD_POST = 3 37 } 38 39 struct tms320c64x_op_mem 40 { 41 uint base; ///< base register 42 uint disp; ///< displacement/offset value 43 uint unit; ///< unit of base and offset register 44 uint scaled; ///< offset scaled 45 uint disptype; ///< displacement type 46 uint direction; ///< direction 47 uint modify; ///< modification 48 } 49 50 struct cs_tms320c64x_op 51 { 52 tms320c64x_op_type type; ///< operand type 53 union 54 { 55 uint reg; ///< register value for REG operand or first register for REGPAIR operand 56 int imm; ///< immediate value for IMM operand 57 tms320c64x_op_mem mem; ///< base/disp value for MEM operand 58 } 59 } 60 61 struct cs_tms320c64x 62 { 63 ubyte op_count; 64 cs_tms320c64x_op[8] operands; ///< operands for this instruction. 65 struct _Anonymous_0 66 { 67 uint reg; 68 uint zero; 69 } 70 71 _Anonymous_0 condition; 72 73 struct _Anonymous_1 74 { 75 uint unit; 76 uint side; 77 uint crosspath; 78 } 79 80 _Anonymous_1 funit; 81 uint parallel; 82 } 83 84 enum tms320c64x_reg 85 { 86 TMS320C64X_REG_INVALID = 0, 87 88 TMS320C64X_REG_AMR = 1, 89 TMS320C64X_REG_CSR = 2, 90 TMS320C64X_REG_DIER = 3, 91 TMS320C64X_REG_DNUM = 4, 92 TMS320C64X_REG_ECR = 5, 93 TMS320C64X_REG_GFPGFR = 6, 94 TMS320C64X_REG_GPLYA = 7, 95 TMS320C64X_REG_GPLYB = 8, 96 TMS320C64X_REG_ICR = 9, 97 TMS320C64X_REG_IER = 10, 98 TMS320C64X_REG_IERR = 11, 99 TMS320C64X_REG_ILC = 12, 100 TMS320C64X_REG_IRP = 13, 101 TMS320C64X_REG_ISR = 14, 102 TMS320C64X_REG_ISTP = 15, 103 TMS320C64X_REG_ITSR = 16, 104 TMS320C64X_REG_NRP = 17, 105 TMS320C64X_REG_NTSR = 18, 106 TMS320C64X_REG_REP = 19, 107 TMS320C64X_REG_RILC = 20, 108 TMS320C64X_REG_SSR = 21, 109 TMS320C64X_REG_TSCH = 22, 110 TMS320C64X_REG_TSCL = 23, 111 TMS320C64X_REG_TSR = 24, 112 TMS320C64X_REG_A0 = 25, 113 TMS320C64X_REG_A1 = 26, 114 TMS320C64X_REG_A2 = 27, 115 TMS320C64X_REG_A3 = 28, 116 TMS320C64X_REG_A4 = 29, 117 TMS320C64X_REG_A5 = 30, 118 TMS320C64X_REG_A6 = 31, 119 TMS320C64X_REG_A7 = 32, 120 TMS320C64X_REG_A8 = 33, 121 TMS320C64X_REG_A9 = 34, 122 TMS320C64X_REG_A10 = 35, 123 TMS320C64X_REG_A11 = 36, 124 TMS320C64X_REG_A12 = 37, 125 TMS320C64X_REG_A13 = 38, 126 TMS320C64X_REG_A14 = 39, 127 TMS320C64X_REG_A15 = 40, 128 TMS320C64X_REG_A16 = 41, 129 TMS320C64X_REG_A17 = 42, 130 TMS320C64X_REG_A18 = 43, 131 TMS320C64X_REG_A19 = 44, 132 TMS320C64X_REG_A20 = 45, 133 TMS320C64X_REG_A21 = 46, 134 TMS320C64X_REG_A22 = 47, 135 TMS320C64X_REG_A23 = 48, 136 TMS320C64X_REG_A24 = 49, 137 TMS320C64X_REG_A25 = 50, 138 TMS320C64X_REG_A26 = 51, 139 TMS320C64X_REG_A27 = 52, 140 TMS320C64X_REG_A28 = 53, 141 TMS320C64X_REG_A29 = 54, 142 TMS320C64X_REG_A30 = 55, 143 TMS320C64X_REG_A31 = 56, 144 TMS320C64X_REG_B0 = 57, 145 TMS320C64X_REG_B1 = 58, 146 TMS320C64X_REG_B2 = 59, 147 TMS320C64X_REG_B3 = 60, 148 TMS320C64X_REG_B4 = 61, 149 TMS320C64X_REG_B5 = 62, 150 TMS320C64X_REG_B6 = 63, 151 TMS320C64X_REG_B7 = 64, 152 TMS320C64X_REG_B8 = 65, 153 TMS320C64X_REG_B9 = 66, 154 TMS320C64X_REG_B10 = 67, 155 TMS320C64X_REG_B11 = 68, 156 TMS320C64X_REG_B12 = 69, 157 TMS320C64X_REG_B13 = 70, 158 TMS320C64X_REG_B14 = 71, 159 TMS320C64X_REG_B15 = 72, 160 TMS320C64X_REG_B16 = 73, 161 TMS320C64X_REG_B17 = 74, 162 TMS320C64X_REG_B18 = 75, 163 TMS320C64X_REG_B19 = 76, 164 TMS320C64X_REG_B20 = 77, 165 TMS320C64X_REG_B21 = 78, 166 TMS320C64X_REG_B22 = 79, 167 TMS320C64X_REG_B23 = 80, 168 TMS320C64X_REG_B24 = 81, 169 TMS320C64X_REG_B25 = 82, 170 TMS320C64X_REG_B26 = 83, 171 TMS320C64X_REG_B27 = 84, 172 TMS320C64X_REG_B28 = 85, 173 TMS320C64X_REG_B29 = 86, 174 TMS320C64X_REG_B30 = 87, 175 TMS320C64X_REG_B31 = 88, 176 TMS320C64X_REG_PCE1 = 89, 177 178 TMS320C64X_REG_ENDING = 90, // <-- mark the end of the list of registers 179 180 // Alias registers 181 TMS320C64X_REG_EFR = TMS320C64X_REG_ECR, 182 TMS320C64X_REG_IFR = TMS320C64X_REG_ISR 183 } 184 185 enum tms320c64x_insn 186 { 187 TMS320C64X_INS_INVALID = 0, 188 189 TMS320C64X_INS_ABS = 1, 190 TMS320C64X_INS_ABS2 = 2, 191 TMS320C64X_INS_ADD = 3, 192 TMS320C64X_INS_ADD2 = 4, 193 TMS320C64X_INS_ADD4 = 5, 194 TMS320C64X_INS_ADDAB = 6, 195 TMS320C64X_INS_ADDAD = 7, 196 TMS320C64X_INS_ADDAH = 8, 197 TMS320C64X_INS_ADDAW = 9, 198 TMS320C64X_INS_ADDK = 10, 199 TMS320C64X_INS_ADDKPC = 11, 200 TMS320C64X_INS_ADDU = 12, 201 TMS320C64X_INS_AND = 13, 202 TMS320C64X_INS_ANDN = 14, 203 TMS320C64X_INS_AVG2 = 15, 204 TMS320C64X_INS_AVGU4 = 16, 205 TMS320C64X_INS_B = 17, 206 TMS320C64X_INS_BDEC = 18, 207 TMS320C64X_INS_BITC4 = 19, 208 TMS320C64X_INS_BNOP = 20, 209 TMS320C64X_INS_BPOS = 21, 210 TMS320C64X_INS_CLR = 22, 211 TMS320C64X_INS_CMPEQ = 23, 212 TMS320C64X_INS_CMPEQ2 = 24, 213 TMS320C64X_INS_CMPEQ4 = 25, 214 TMS320C64X_INS_CMPGT = 26, 215 TMS320C64X_INS_CMPGT2 = 27, 216 TMS320C64X_INS_CMPGTU4 = 28, 217 TMS320C64X_INS_CMPLT = 29, 218 TMS320C64X_INS_CMPLTU = 30, 219 TMS320C64X_INS_DEAL = 31, 220 TMS320C64X_INS_DOTP2 = 32, 221 TMS320C64X_INS_DOTPN2 = 33, 222 TMS320C64X_INS_DOTPNRSU2 = 34, 223 TMS320C64X_INS_DOTPRSU2 = 35, 224 TMS320C64X_INS_DOTPSU4 = 36, 225 TMS320C64X_INS_DOTPU4 = 37, 226 TMS320C64X_INS_EXT = 38, 227 TMS320C64X_INS_EXTU = 39, 228 TMS320C64X_INS_GMPGTU = 40, 229 TMS320C64X_INS_GMPY4 = 41, 230 TMS320C64X_INS_LDB = 42, 231 TMS320C64X_INS_LDBU = 43, 232 TMS320C64X_INS_LDDW = 44, 233 TMS320C64X_INS_LDH = 45, 234 TMS320C64X_INS_LDHU = 46, 235 TMS320C64X_INS_LDNDW = 47, 236 TMS320C64X_INS_LDNW = 48, 237 TMS320C64X_INS_LDW = 49, 238 TMS320C64X_INS_LMBD = 50, 239 TMS320C64X_INS_MAX2 = 51, 240 TMS320C64X_INS_MAXU4 = 52, 241 TMS320C64X_INS_MIN2 = 53, 242 TMS320C64X_INS_MINU4 = 54, 243 TMS320C64X_INS_MPY = 55, 244 TMS320C64X_INS_MPY2 = 56, 245 TMS320C64X_INS_MPYH = 57, 246 TMS320C64X_INS_MPYHI = 58, 247 TMS320C64X_INS_MPYHIR = 59, 248 TMS320C64X_INS_MPYHL = 60, 249 TMS320C64X_INS_MPYHLU = 61, 250 TMS320C64X_INS_MPYHSLU = 62, 251 TMS320C64X_INS_MPYHSU = 63, 252 TMS320C64X_INS_MPYHU = 64, 253 TMS320C64X_INS_MPYHULS = 65, 254 TMS320C64X_INS_MPYHUS = 66, 255 TMS320C64X_INS_MPYLH = 67, 256 TMS320C64X_INS_MPYLHU = 68, 257 TMS320C64X_INS_MPYLI = 69, 258 TMS320C64X_INS_MPYLIR = 70, 259 TMS320C64X_INS_MPYLSHU = 71, 260 TMS320C64X_INS_MPYLUHS = 72, 261 TMS320C64X_INS_MPYSU = 73, 262 TMS320C64X_INS_MPYSU4 = 74, 263 TMS320C64X_INS_MPYU = 75, 264 TMS320C64X_INS_MPYU4 = 76, 265 TMS320C64X_INS_MPYUS = 77, 266 TMS320C64X_INS_MVC = 78, 267 TMS320C64X_INS_MVD = 79, 268 TMS320C64X_INS_MVK = 80, 269 TMS320C64X_INS_MVKL = 81, 270 TMS320C64X_INS_MVKLH = 82, 271 TMS320C64X_INS_NOP = 83, 272 TMS320C64X_INS_NORM = 84, 273 TMS320C64X_INS_OR = 85, 274 TMS320C64X_INS_PACK2 = 86, 275 TMS320C64X_INS_PACKH2 = 87, 276 TMS320C64X_INS_PACKH4 = 88, 277 TMS320C64X_INS_PACKHL2 = 89, 278 TMS320C64X_INS_PACKL4 = 90, 279 TMS320C64X_INS_PACKLH2 = 91, 280 TMS320C64X_INS_ROTL = 92, 281 TMS320C64X_INS_SADD = 93, 282 TMS320C64X_INS_SADD2 = 94, 283 TMS320C64X_INS_SADDU4 = 95, 284 TMS320C64X_INS_SADDUS2 = 96, 285 TMS320C64X_INS_SAT = 97, 286 TMS320C64X_INS_SET = 98, 287 TMS320C64X_INS_SHFL = 99, 288 TMS320C64X_INS_SHL = 100, 289 TMS320C64X_INS_SHLMB = 101, 290 TMS320C64X_INS_SHR = 102, 291 TMS320C64X_INS_SHR2 = 103, 292 TMS320C64X_INS_SHRMB = 104, 293 TMS320C64X_INS_SHRU = 105, 294 TMS320C64X_INS_SHRU2 = 106, 295 TMS320C64X_INS_SMPY = 107, 296 TMS320C64X_INS_SMPY2 = 108, 297 TMS320C64X_INS_SMPYH = 109, 298 TMS320C64X_INS_SMPYHL = 110, 299 TMS320C64X_INS_SMPYLH = 111, 300 TMS320C64X_INS_SPACK2 = 112, 301 TMS320C64X_INS_SPACKU4 = 113, 302 TMS320C64X_INS_SSHL = 114, 303 TMS320C64X_INS_SSHVL = 115, 304 TMS320C64X_INS_SSHVR = 116, 305 TMS320C64X_INS_SSUB = 117, 306 TMS320C64X_INS_STB = 118, 307 TMS320C64X_INS_STDW = 119, 308 TMS320C64X_INS_STH = 120, 309 TMS320C64X_INS_STNDW = 121, 310 TMS320C64X_INS_STNW = 122, 311 TMS320C64X_INS_STW = 123, 312 TMS320C64X_INS_SUB = 124, 313 TMS320C64X_INS_SUB2 = 125, 314 TMS320C64X_INS_SUB4 = 126, 315 TMS320C64X_INS_SUBAB = 127, 316 TMS320C64X_INS_SUBABS4 = 128, 317 TMS320C64X_INS_SUBAH = 129, 318 TMS320C64X_INS_SUBAW = 130, 319 TMS320C64X_INS_SUBC = 131, 320 TMS320C64X_INS_SUBU = 132, 321 TMS320C64X_INS_SWAP4 = 133, 322 TMS320C64X_INS_UNPKHU4 = 134, 323 TMS320C64X_INS_UNPKLU4 = 135, 324 TMS320C64X_INS_XOR = 136, 325 TMS320C64X_INS_XPND2 = 137, 326 TMS320C64X_INS_XPND4 = 138, 327 // Aliases 328 TMS320C64X_INS_IDLE = 139, 329 TMS320C64X_INS_MV = 140, 330 TMS320C64X_INS_NEG = 141, 331 TMS320C64X_INS_NOT = 142, 332 TMS320C64X_INS_SWAP2 = 143, 333 TMS320C64X_INS_ZERO = 144, 334 335 TMS320C64X_INS_ENDING = 145 // <-- mark the end of the list of instructions 336 } 337 338 enum tms320c64x_insn_group 339 { 340 TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID 341 342 TMS320C64X_GRP_JUMP = 1, ///< = CS_GRP_JUMP 343 344 TMS320C64X_GRP_FUNIT_D = 128, 345 TMS320C64X_GRP_FUNIT_L = 129, 346 TMS320C64X_GRP_FUNIT_M = 130, 347 TMS320C64X_GRP_FUNIT_S = 131, 348 TMS320C64X_GRP_FUNIT_NO = 132, 349 350 TMS320C64X_GRP_ENDING = 133 // <-- mark the end of the list of groups 351 } 352 353 enum tms320c64x_funit 354 { 355 TMS320C64X_FUNIT_INVALID = 0, 356 TMS320C64X_FUNIT_D = 1, 357 TMS320C64X_FUNIT_L = 2, 358 TMS320C64X_FUNIT_M = 3, 359 TMS320C64X_FUNIT_S = 4, 360 TMS320C64X_FUNIT_NO = 5 361 }