1 module capstone.sparc; 2 3 extern (C): 4 5 /* Capstone Disassembly Engine */ 6 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ 7 8 // GCC SPARC toolchain has a default macro called "sparc" which breaks 9 // compilation 10 11 /// Enums corresponding to Sparc condition codes, both icc's and fcc's. 12 enum sparc_cc 13 { 14 SPARC_CC_INVALID = 0, ///< invalid CC (default) 15 // Integer condition codes 16 SPARC_CC_ICC_A = 8 + 256, ///< Always 17 SPARC_CC_ICC_N = 0 + 256, ///< Never 18 SPARC_CC_ICC_NE = 9 + 256, ///< Not Equal 19 SPARC_CC_ICC_E = 1 + 256, ///< Equal 20 SPARC_CC_ICC_G = 10 + 256, ///< Greater 21 SPARC_CC_ICC_LE = 2 + 256, ///< Less or Equal 22 SPARC_CC_ICC_GE = 11 + 256, ///< Greater or Equal 23 SPARC_CC_ICC_L = 3 + 256, ///< Less 24 SPARC_CC_ICC_GU = 12 + 256, ///< Greater Unsigned 25 SPARC_CC_ICC_LEU = 4 + 256, ///< Less or Equal Unsigned 26 SPARC_CC_ICC_CC = 13 + 256, ///< Carry Clear/Great or Equal Unsigned 27 SPARC_CC_ICC_CS = 5 + 256, ///< Carry Set/Less Unsigned 28 SPARC_CC_ICC_POS = 14 + 256, ///< Positive 29 SPARC_CC_ICC_NEG = 6 + 256, ///< Negative 30 SPARC_CC_ICC_VC = 15 + 256, ///< Overflow Clear 31 SPARC_CC_ICC_VS = 7 + 256, ///< Overflow Set 32 33 // Floating condition codes 34 SPARC_CC_FCC_A = 8 + 16 + 256, ///< Always 35 SPARC_CC_FCC_N = 0 + 16 + 256, ///< Never 36 SPARC_CC_FCC_U = 7 + 16 + 256, ///< Unordered 37 SPARC_CC_FCC_G = 6 + 16 + 256, ///< Greater 38 SPARC_CC_FCC_UG = 5 + 16 + 256, ///< Unordered or Greater 39 SPARC_CC_FCC_L = 4 + 16 + 256, ///< Less 40 SPARC_CC_FCC_UL = 3 + 16 + 256, ///< Unordered or Less 41 SPARC_CC_FCC_LG = 2 + 16 + 256, ///< Less or Greater 42 SPARC_CC_FCC_NE = 1 + 16 + 256, ///< Not Equal 43 SPARC_CC_FCC_E = 9 + 16 + 256, ///< Equal 44 SPARC_CC_FCC_UE = 10 + 16 + 256, ///< Unordered or Equal 45 SPARC_CC_FCC_GE = 11 + 16 + 256, ///< Greater or Equal 46 SPARC_CC_FCC_UGE = 12 + 16 + 256, ///< Unordered or Greater or Equal 47 SPARC_CC_FCC_LE = 13 + 16 + 256, ///< Less or Equal 48 SPARC_CC_FCC_ULE = 14 + 16 + 256, ///< Unordered or Less or Equal 49 SPARC_CC_FCC_O = 15 + 16 + 256 ///< Ordered 50 } 51 52 /// Branch hint 53 enum sparc_hint 54 { 55 SPARC_HINT_INVALID = 0, ///< no hint 56 SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction 57 SPARC_HINT_PT = 1 << 1, ///< branch taken 58 SPARC_HINT_PN = 1 << 2 ///< branch NOT taken 59 } 60 61 /// Operand type for instruction's operands 62 enum sparc_op_type 63 { 64 SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 65 SPARC_OP_REG = 1, ///< = CS_OP_REG (Register operand). 66 SPARC_OP_IMM = 2, ///< = CS_OP_IMM (Immediate operand). 67 SPARC_OP_MEM = 3 ///< = CS_OP_MEM (Memory operand). 68 } 69 70 /// SPARC registers 71 enum sparc_reg 72 { 73 SPARC_REG_INVALID = 0, 74 75 SPARC_REG_F0 = 1, 76 SPARC_REG_F1 = 2, 77 SPARC_REG_F2 = 3, 78 SPARC_REG_F3 = 4, 79 SPARC_REG_F4 = 5, 80 SPARC_REG_F5 = 6, 81 SPARC_REG_F6 = 7, 82 SPARC_REG_F7 = 8, 83 SPARC_REG_F8 = 9, 84 SPARC_REG_F9 = 10, 85 SPARC_REG_F10 = 11, 86 SPARC_REG_F11 = 12, 87 SPARC_REG_F12 = 13, 88 SPARC_REG_F13 = 14, 89 SPARC_REG_F14 = 15, 90 SPARC_REG_F15 = 16, 91 SPARC_REG_F16 = 17, 92 SPARC_REG_F17 = 18, 93 SPARC_REG_F18 = 19, 94 SPARC_REG_F19 = 20, 95 SPARC_REG_F20 = 21, 96 SPARC_REG_F21 = 22, 97 SPARC_REG_F22 = 23, 98 SPARC_REG_F23 = 24, 99 SPARC_REG_F24 = 25, 100 SPARC_REG_F25 = 26, 101 SPARC_REG_F26 = 27, 102 SPARC_REG_F27 = 28, 103 SPARC_REG_F28 = 29, 104 SPARC_REG_F29 = 30, 105 SPARC_REG_F30 = 31, 106 SPARC_REG_F31 = 32, 107 SPARC_REG_F32 = 33, 108 SPARC_REG_F34 = 34, 109 SPARC_REG_F36 = 35, 110 SPARC_REG_F38 = 36, 111 SPARC_REG_F40 = 37, 112 SPARC_REG_F42 = 38, 113 SPARC_REG_F44 = 39, 114 SPARC_REG_F46 = 40, 115 SPARC_REG_F48 = 41, 116 SPARC_REG_F50 = 42, 117 SPARC_REG_F52 = 43, 118 SPARC_REG_F54 = 44, 119 SPARC_REG_F56 = 45, 120 SPARC_REG_F58 = 46, 121 SPARC_REG_F60 = 47, 122 SPARC_REG_F62 = 48, 123 SPARC_REG_FCC0 = 49, // Floating condition codes 124 SPARC_REG_FCC1 = 50, 125 SPARC_REG_FCC2 = 51, 126 SPARC_REG_FCC3 = 52, 127 SPARC_REG_FP = 53, 128 SPARC_REG_G0 = 54, 129 SPARC_REG_G1 = 55, 130 SPARC_REG_G2 = 56, 131 SPARC_REG_G3 = 57, 132 SPARC_REG_G4 = 58, 133 SPARC_REG_G5 = 59, 134 SPARC_REG_G6 = 60, 135 SPARC_REG_G7 = 61, 136 SPARC_REG_I0 = 62, 137 SPARC_REG_I1 = 63, 138 SPARC_REG_I2 = 64, 139 SPARC_REG_I3 = 65, 140 SPARC_REG_I4 = 66, 141 SPARC_REG_I5 = 67, 142 SPARC_REG_I7 = 68, 143 SPARC_REG_ICC = 69, // Integer condition codes 144 SPARC_REG_L0 = 70, 145 SPARC_REG_L1 = 71, 146 SPARC_REG_L2 = 72, 147 SPARC_REG_L3 = 73, 148 SPARC_REG_L4 = 74, 149 SPARC_REG_L5 = 75, 150 SPARC_REG_L6 = 76, 151 SPARC_REG_L7 = 77, 152 SPARC_REG_O0 = 78, 153 SPARC_REG_O1 = 79, 154 SPARC_REG_O2 = 80, 155 SPARC_REG_O3 = 81, 156 SPARC_REG_O4 = 82, 157 SPARC_REG_O5 = 83, 158 SPARC_REG_O7 = 84, 159 SPARC_REG_SP = 85, 160 SPARC_REG_Y = 86, 161 162 // special register 163 SPARC_REG_XCC = 87, 164 165 SPARC_REG_ENDING = 88, // <-- mark the end of the list of registers 166 167 // extras 168 SPARC_REG_O6 = SPARC_REG_SP, 169 SPARC_REG_I6 = SPARC_REG_FP 170 } 171 172 /// Instruction's operand referring to memory 173 /// This is associated with SPARC_OP_MEM operand type above 174 struct sparc_op_mem 175 { 176 ubyte base; ///< base register, can be safely interpreted as 177 ///< a value of type `sparc_reg`, but it is only 178 ///< one byte wide 179 ubyte index; ///< index register, same conditions apply here 180 int disp; ///< displacement/offset value 181 } 182 183 /// Instruction operand 184 struct cs_sparc_op 185 { 186 sparc_op_type type; ///< operand type 187 union 188 { 189 sparc_reg reg; ///< register value for REG operand 190 long imm; ///< immediate value for IMM operand 191 sparc_op_mem mem; ///< base/disp value for MEM operand 192 } 193 } 194 195 /// Instruction structure 196 struct cs_sparc 197 { 198 sparc_cc cc; ///< code condition for this insn 199 sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint. 200 /// Number of operands of this instruction, 201 /// or 0 when instruction has no operand. 202 ubyte op_count; 203 cs_sparc_op[4] operands; ///< operands for this instruction. 204 } 205 206 /// SPARC instruction 207 enum sparc_insn 208 { 209 SPARC_INS_INVALID = 0, 210 211 SPARC_INS_ADDCC = 1, 212 SPARC_INS_ADDX = 2, 213 SPARC_INS_ADDXCC = 3, 214 SPARC_INS_ADDXC = 4, 215 SPARC_INS_ADDXCCC = 5, 216 SPARC_INS_ADD = 6, 217 SPARC_INS_ALIGNADDR = 7, 218 SPARC_INS_ALIGNADDRL = 8, 219 SPARC_INS_ANDCC = 9, 220 SPARC_INS_ANDNCC = 10, 221 SPARC_INS_ANDN = 11, 222 SPARC_INS_AND = 12, 223 SPARC_INS_ARRAY16 = 13, 224 SPARC_INS_ARRAY32 = 14, 225 SPARC_INS_ARRAY8 = 15, 226 SPARC_INS_B = 16, 227 SPARC_INS_JMP = 17, 228 SPARC_INS_BMASK = 18, 229 SPARC_INS_FB = 19, 230 SPARC_INS_BRGEZ = 20, 231 SPARC_INS_BRGZ = 21, 232 SPARC_INS_BRLEZ = 22, 233 SPARC_INS_BRLZ = 23, 234 SPARC_INS_BRNZ = 24, 235 SPARC_INS_BRZ = 25, 236 SPARC_INS_BSHUFFLE = 26, 237 SPARC_INS_CALL = 27, 238 SPARC_INS_CASX = 28, 239 SPARC_INS_CAS = 29, 240 SPARC_INS_CMASK16 = 30, 241 SPARC_INS_CMASK32 = 31, 242 SPARC_INS_CMASK8 = 32, 243 SPARC_INS_CMP = 33, 244 SPARC_INS_EDGE16 = 34, 245 SPARC_INS_EDGE16L = 35, 246 SPARC_INS_EDGE16LN = 36, 247 SPARC_INS_EDGE16N = 37, 248 SPARC_INS_EDGE32 = 38, 249 SPARC_INS_EDGE32L = 39, 250 SPARC_INS_EDGE32LN = 40, 251 SPARC_INS_EDGE32N = 41, 252 SPARC_INS_EDGE8 = 42, 253 SPARC_INS_EDGE8L = 43, 254 SPARC_INS_EDGE8LN = 44, 255 SPARC_INS_EDGE8N = 45, 256 SPARC_INS_FABSD = 46, 257 SPARC_INS_FABSQ = 47, 258 SPARC_INS_FABSS = 48, 259 SPARC_INS_FADDD = 49, 260 SPARC_INS_FADDQ = 50, 261 SPARC_INS_FADDS = 51, 262 SPARC_INS_FALIGNDATA = 52, 263 SPARC_INS_FAND = 53, 264 SPARC_INS_FANDNOT1 = 54, 265 SPARC_INS_FANDNOT1S = 55, 266 SPARC_INS_FANDNOT2 = 56, 267 SPARC_INS_FANDNOT2S = 57, 268 SPARC_INS_FANDS = 58, 269 SPARC_INS_FCHKSM16 = 59, 270 SPARC_INS_FCMPD = 60, 271 SPARC_INS_FCMPEQ16 = 61, 272 SPARC_INS_FCMPEQ32 = 62, 273 SPARC_INS_FCMPGT16 = 63, 274 SPARC_INS_FCMPGT32 = 64, 275 SPARC_INS_FCMPLE16 = 65, 276 SPARC_INS_FCMPLE32 = 66, 277 SPARC_INS_FCMPNE16 = 67, 278 SPARC_INS_FCMPNE32 = 68, 279 SPARC_INS_FCMPQ = 69, 280 SPARC_INS_FCMPS = 70, 281 SPARC_INS_FDIVD = 71, 282 SPARC_INS_FDIVQ = 72, 283 SPARC_INS_FDIVS = 73, 284 SPARC_INS_FDMULQ = 74, 285 SPARC_INS_FDTOI = 75, 286 SPARC_INS_FDTOQ = 76, 287 SPARC_INS_FDTOS = 77, 288 SPARC_INS_FDTOX = 78, 289 SPARC_INS_FEXPAND = 79, 290 SPARC_INS_FHADDD = 80, 291 SPARC_INS_FHADDS = 81, 292 SPARC_INS_FHSUBD = 82, 293 SPARC_INS_FHSUBS = 83, 294 SPARC_INS_FITOD = 84, 295 SPARC_INS_FITOQ = 85, 296 SPARC_INS_FITOS = 86, 297 SPARC_INS_FLCMPD = 87, 298 SPARC_INS_FLCMPS = 88, 299 SPARC_INS_FLUSHW = 89, 300 SPARC_INS_FMEAN16 = 90, 301 SPARC_INS_FMOVD = 91, 302 SPARC_INS_FMOVQ = 92, 303 SPARC_INS_FMOVRDGEZ = 93, 304 SPARC_INS_FMOVRQGEZ = 94, 305 SPARC_INS_FMOVRSGEZ = 95, 306 SPARC_INS_FMOVRDGZ = 96, 307 SPARC_INS_FMOVRQGZ = 97, 308 SPARC_INS_FMOVRSGZ = 98, 309 SPARC_INS_FMOVRDLEZ = 99, 310 SPARC_INS_FMOVRQLEZ = 100, 311 SPARC_INS_FMOVRSLEZ = 101, 312 SPARC_INS_FMOVRDLZ = 102, 313 SPARC_INS_FMOVRQLZ = 103, 314 SPARC_INS_FMOVRSLZ = 104, 315 SPARC_INS_FMOVRDNZ = 105, 316 SPARC_INS_FMOVRQNZ = 106, 317 SPARC_INS_FMOVRSNZ = 107, 318 SPARC_INS_FMOVRDZ = 108, 319 SPARC_INS_FMOVRQZ = 109, 320 SPARC_INS_FMOVRSZ = 110, 321 SPARC_INS_FMOVS = 111, 322 SPARC_INS_FMUL8SUX16 = 112, 323 SPARC_INS_FMUL8ULX16 = 113, 324 SPARC_INS_FMUL8X16 = 114, 325 SPARC_INS_FMUL8X16AL = 115, 326 SPARC_INS_FMUL8X16AU = 116, 327 SPARC_INS_FMULD = 117, 328 SPARC_INS_FMULD8SUX16 = 118, 329 SPARC_INS_FMULD8ULX16 = 119, 330 SPARC_INS_FMULQ = 120, 331 SPARC_INS_FMULS = 121, 332 SPARC_INS_FNADDD = 122, 333 SPARC_INS_FNADDS = 123, 334 SPARC_INS_FNAND = 124, 335 SPARC_INS_FNANDS = 125, 336 SPARC_INS_FNEGD = 126, 337 SPARC_INS_FNEGQ = 127, 338 SPARC_INS_FNEGS = 128, 339 SPARC_INS_FNHADDD = 129, 340 SPARC_INS_FNHADDS = 130, 341 SPARC_INS_FNOR = 131, 342 SPARC_INS_FNORS = 132, 343 SPARC_INS_FNOT1 = 133, 344 SPARC_INS_FNOT1S = 134, 345 SPARC_INS_FNOT2 = 135, 346 SPARC_INS_FNOT2S = 136, 347 SPARC_INS_FONE = 137, 348 SPARC_INS_FONES = 138, 349 SPARC_INS_FOR = 139, 350 SPARC_INS_FORNOT1 = 140, 351 SPARC_INS_FORNOT1S = 141, 352 SPARC_INS_FORNOT2 = 142, 353 SPARC_INS_FORNOT2S = 143, 354 SPARC_INS_FORS = 144, 355 SPARC_INS_FPACK16 = 145, 356 SPARC_INS_FPACK32 = 146, 357 SPARC_INS_FPACKFIX = 147, 358 SPARC_INS_FPADD16 = 148, 359 SPARC_INS_FPADD16S = 149, 360 SPARC_INS_FPADD32 = 150, 361 SPARC_INS_FPADD32S = 151, 362 SPARC_INS_FPADD64 = 152, 363 SPARC_INS_FPMERGE = 153, 364 SPARC_INS_FPSUB16 = 154, 365 SPARC_INS_FPSUB16S = 155, 366 SPARC_INS_FPSUB32 = 156, 367 SPARC_INS_FPSUB32S = 157, 368 SPARC_INS_FQTOD = 158, 369 SPARC_INS_FQTOI = 159, 370 SPARC_INS_FQTOS = 160, 371 SPARC_INS_FQTOX = 161, 372 SPARC_INS_FSLAS16 = 162, 373 SPARC_INS_FSLAS32 = 163, 374 SPARC_INS_FSLL16 = 164, 375 SPARC_INS_FSLL32 = 165, 376 SPARC_INS_FSMULD = 166, 377 SPARC_INS_FSQRTD = 167, 378 SPARC_INS_FSQRTQ = 168, 379 SPARC_INS_FSQRTS = 169, 380 SPARC_INS_FSRA16 = 170, 381 SPARC_INS_FSRA32 = 171, 382 SPARC_INS_FSRC1 = 172, 383 SPARC_INS_FSRC1S = 173, 384 SPARC_INS_FSRC2 = 174, 385 SPARC_INS_FSRC2S = 175, 386 SPARC_INS_FSRL16 = 176, 387 SPARC_INS_FSRL32 = 177, 388 SPARC_INS_FSTOD = 178, 389 SPARC_INS_FSTOI = 179, 390 SPARC_INS_FSTOQ = 180, 391 SPARC_INS_FSTOX = 181, 392 SPARC_INS_FSUBD = 182, 393 SPARC_INS_FSUBQ = 183, 394 SPARC_INS_FSUBS = 184, 395 SPARC_INS_FXNOR = 185, 396 SPARC_INS_FXNORS = 186, 397 SPARC_INS_FXOR = 187, 398 SPARC_INS_FXORS = 188, 399 SPARC_INS_FXTOD = 189, 400 SPARC_INS_FXTOQ = 190, 401 SPARC_INS_FXTOS = 191, 402 SPARC_INS_FZERO = 192, 403 SPARC_INS_FZEROS = 193, 404 SPARC_INS_JMPL = 194, 405 SPARC_INS_LDD = 195, 406 SPARC_INS_LD = 196, 407 SPARC_INS_LDQ = 197, 408 SPARC_INS_LDSB = 198, 409 SPARC_INS_LDSH = 199, 410 SPARC_INS_LDSW = 200, 411 SPARC_INS_LDUB = 201, 412 SPARC_INS_LDUH = 202, 413 SPARC_INS_LDX = 203, 414 SPARC_INS_LZCNT = 204, 415 SPARC_INS_MEMBAR = 205, 416 SPARC_INS_MOVDTOX = 206, 417 SPARC_INS_MOV = 207, 418 SPARC_INS_MOVRGEZ = 208, 419 SPARC_INS_MOVRGZ = 209, 420 SPARC_INS_MOVRLEZ = 210, 421 SPARC_INS_MOVRLZ = 211, 422 SPARC_INS_MOVRNZ = 212, 423 SPARC_INS_MOVRZ = 213, 424 SPARC_INS_MOVSTOSW = 214, 425 SPARC_INS_MOVSTOUW = 215, 426 SPARC_INS_MULX = 216, 427 SPARC_INS_NOP = 217, 428 SPARC_INS_ORCC = 218, 429 SPARC_INS_ORNCC = 219, 430 SPARC_INS_ORN = 220, 431 SPARC_INS_OR = 221, 432 SPARC_INS_PDIST = 222, 433 SPARC_INS_PDISTN = 223, 434 SPARC_INS_POPC = 224, 435 SPARC_INS_RD = 225, 436 SPARC_INS_RESTORE = 226, 437 SPARC_INS_RETT = 227, 438 SPARC_INS_SAVE = 228, 439 SPARC_INS_SDIVCC = 229, 440 SPARC_INS_SDIVX = 230, 441 SPARC_INS_SDIV = 231, 442 SPARC_INS_SETHI = 232, 443 SPARC_INS_SHUTDOWN = 233, 444 SPARC_INS_SIAM = 234, 445 SPARC_INS_SLLX = 235, 446 SPARC_INS_SLL = 236, 447 SPARC_INS_SMULCC = 237, 448 SPARC_INS_SMUL = 238, 449 SPARC_INS_SRAX = 239, 450 SPARC_INS_SRA = 240, 451 SPARC_INS_SRLX = 241, 452 SPARC_INS_SRL = 242, 453 SPARC_INS_STBAR = 243, 454 SPARC_INS_STB = 244, 455 SPARC_INS_STD = 245, 456 SPARC_INS_ST = 246, 457 SPARC_INS_STH = 247, 458 SPARC_INS_STQ = 248, 459 SPARC_INS_STX = 249, 460 SPARC_INS_SUBCC = 250, 461 SPARC_INS_SUBX = 251, 462 SPARC_INS_SUBXCC = 252, 463 SPARC_INS_SUB = 253, 464 SPARC_INS_SWAP = 254, 465 SPARC_INS_TADDCCTV = 255, 466 SPARC_INS_TADDCC = 256, 467 SPARC_INS_T = 257, 468 SPARC_INS_TSUBCCTV = 258, 469 SPARC_INS_TSUBCC = 259, 470 SPARC_INS_UDIVCC = 260, 471 SPARC_INS_UDIVX = 261, 472 SPARC_INS_UDIV = 262, 473 SPARC_INS_UMULCC = 263, 474 SPARC_INS_UMULXHI = 264, 475 SPARC_INS_UMUL = 265, 476 SPARC_INS_UNIMP = 266, 477 SPARC_INS_FCMPED = 267, 478 SPARC_INS_FCMPEQ = 268, 479 SPARC_INS_FCMPES = 269, 480 SPARC_INS_WR = 270, 481 SPARC_INS_XMULX = 271, 482 SPARC_INS_XMULXHI = 272, 483 SPARC_INS_XNORCC = 273, 484 SPARC_INS_XNOR = 274, 485 SPARC_INS_XORCC = 275, 486 SPARC_INS_XOR = 276, 487 488 // alias instructions 489 SPARC_INS_RET = 277, 490 SPARC_INS_RETL = 278, 491 492 SPARC_INS_ENDING = 279 // <-- mark the end of the list of instructions 493 } 494 495 /// Group of SPARC instructions 496 enum sparc_insn_group 497 { 498 SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID 499 500 // Generic groups 501 // all jump instructions (conditional+direct+indirect jumps) 502 SPARC_GRP_JUMP = 1, ///< = CS_GRP_JUMP 503 504 // Architecture-specific groups 505 SPARC_GRP_HARDQUAD = 128, 506 SPARC_GRP_V9 = 129, 507 SPARC_GRP_VIS = 130, 508 SPARC_GRP_VIS2 = 131, 509 SPARC_GRP_VIS3 = 132, 510 SPARC_GRP_32BIT = 133, 511 SPARC_GRP_64BIT = 134, 512 513 SPARC_GRP_ENDING = 135 // <-- mark the end of the list of groups 514 }