1 module capstone.arm64; 2 3 extern (C): 4 5 /* Capstone Disassembly Engine */ 6 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 7 8 /// ARM64 shift type 9 enum arm64_shifter 10 { 11 ARM64_SFT_INVALID = 0, 12 ARM64_SFT_LSL = 1, 13 ARM64_SFT_MSL = 2, 14 ARM64_SFT_LSR = 3, 15 ARM64_SFT_ASR = 4, 16 ARM64_SFT_ROR = 5 17 } 18 19 /// ARM64 extender type 20 enum arm64_extender 21 { 22 ARM64_EXT_INVALID = 0, 23 ARM64_EXT_UXTB = 1, 24 ARM64_EXT_UXTH = 2, 25 ARM64_EXT_UXTW = 3, 26 ARM64_EXT_UXTX = 4, 27 ARM64_EXT_SXTB = 5, 28 ARM64_EXT_SXTH = 6, 29 ARM64_EXT_SXTW = 7, 30 ARM64_EXT_SXTX = 8 31 } 32 33 /// ARM64 condition code 34 enum arm64_cc 35 { 36 ARM64_CC_INVALID = 0, 37 ARM64_CC_EQ = 1, ///< Equal 38 ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered 39 ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered 40 ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than 41 ARM64_CC_MI = 5, ///< Minus, negative: Less than 42 ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered 43 ARM64_CC_VS = 7, ///< Overflow: Unordered 44 ARM64_CC_VC = 8, ///< No overflow: Ordered 45 ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered 46 ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal 47 ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal 48 ARM64_CC_LT = 12, ///< Less than: Less than, or unordered 49 ARM64_CC_GT = 13, ///< Signed greater than: Greater than 50 ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered 51 ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) 52 ARM64_CC_NV = 16 ///< Always (unconditional): Always (unconditional) 53 //< Note the NV exists purely to disassemble 0b1111. Execution 54 //< is "always". 55 } 56 57 /// System registers 58 enum arm64_sysreg 59 { 60 // System registers for MRS 61 ARM64_SYSREG_INVALID = 0, 62 ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 63 ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 64 ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 65 ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 66 ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 67 ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 68 ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 69 ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 70 ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 71 ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 72 ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 73 ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 74 ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 75 ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 76 ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 77 ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 78 ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 79 ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 80 ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 81 ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 82 ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 83 ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 84 ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 85 ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 86 ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 87 ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 88 ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 89 ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 90 ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 91 ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 92 ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 93 ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 94 ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 95 ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 96 ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 97 ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 98 ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 99 ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 100 ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 101 ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 102 ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 103 ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 104 ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 105 ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 106 ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 107 ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 108 ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 109 ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 110 111 // Trace registers 112 ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000 113 ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 114 ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 115 ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 116 ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 117 ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 118 ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 119 ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 120 ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 121 ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 122 ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 123 ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 124 ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 125 ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 126 ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 127 ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 128 ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 129 ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 130 ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 131 ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110 132 ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 133 ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 134 ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 135 ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 136 ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 137 ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 138 ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 139 ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 140 ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 141 ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 142 ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 143 ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 144 ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 145 ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 146 ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 147 ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 148 149 // GICv3 registers 150 ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 151 ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 152 ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 153 ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 154 ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 155 ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 156 ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 157 ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 158 } 159 160 enum arm64_msr_reg 161 { 162 // System registers for MSR 163 ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 164 ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 165 ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 166 167 // Trace Registers 168 ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 169 ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110 170 171 // GICv3 registers 172 ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 173 ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 174 ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 175 ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 176 ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 177 ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 178 } 179 180 /// System PState Field (MSR instruction) 181 enum arm64_pstate 182 { 183 ARM64_PSTATE_INVALID = 0, 184 ARM64_PSTATE_SPSEL = 0x05, 185 ARM64_PSTATE_DAIFSET = 0x1e, 186 ARM64_PSTATE_DAIFCLR = 0x1f 187 } 188 189 /// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) 190 enum arm64_vas 191 { 192 ARM64_VAS_INVALID = 0, 193 ARM64_VAS_8B = 1, 194 ARM64_VAS_16B = 2, 195 ARM64_VAS_4H = 3, 196 ARM64_VAS_8H = 4, 197 ARM64_VAS_2S = 5, 198 ARM64_VAS_4S = 6, 199 ARM64_VAS_1D = 7, 200 ARM64_VAS_2D = 8, 201 ARM64_VAS_1Q = 9 202 } 203 204 /// Vector element size specifier 205 enum arm64_vess 206 { 207 ARM64_VESS_INVALID = 0, 208 ARM64_VESS_B = 1, 209 ARM64_VESS_H = 2, 210 ARM64_VESS_S = 3, 211 ARM64_VESS_D = 4 212 } 213 214 /// Memory barrier operands 215 enum arm64_barrier_op 216 { 217 ARM64_BARRIER_INVALID = 0, 218 ARM64_BARRIER_OSHLD = 0x1, 219 ARM64_BARRIER_OSHST = 0x2, 220 ARM64_BARRIER_OSH = 0x3, 221 ARM64_BARRIER_NSHLD = 0x5, 222 ARM64_BARRIER_NSHST = 0x6, 223 ARM64_BARRIER_NSH = 0x7, 224 ARM64_BARRIER_ISHLD = 0x9, 225 ARM64_BARRIER_ISHST = 0xa, 226 ARM64_BARRIER_ISH = 0xb, 227 ARM64_BARRIER_LD = 0xd, 228 ARM64_BARRIER_ST = 0xe, 229 ARM64_BARRIER_SY = 0xf 230 } 231 232 /// Operand type for instruction's operands 233 enum arm64_op_type 234 { 235 ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 236 ARM64_OP_REG = 1, ///< = CS_OP_REG (Register operand). 237 ARM64_OP_IMM = 2, ///< = CS_OP_IMM (Immediate operand). 238 ARM64_OP_MEM = 3, ///< = CS_OP_MEM (Memory operand). 239 ARM64_OP_FP = 4, ///< = CS_OP_FP (Floating-Point operand). 240 ARM64_OP_CIMM = 64, ///< C-Immediate 241 ARM64_OP_REG_MRS = 65, ///< MRS register operand. 242 ARM64_OP_REG_MSR = 66, ///< MSR register operand. 243 ARM64_OP_PSTATE = 67, ///< PState operand. 244 ARM64_OP_SYS = 68, ///< SYS operand for IC/DC/AT/TLBI instructions. 245 ARM64_OP_PREFETCH = 69, ///< Prefetch operand (PRFM). 246 ARM64_OP_BARRIER = 70 ///< Memory barrier operand (ISB/DMB/DSB instructions). 247 } 248 249 /// TLBI operations 250 enum arm64_tlbi_op 251 { 252 ARM64_TLBI_INVALID = 0, 253 ARM64_TLBI_VMALLE1IS = 1, 254 ARM64_TLBI_VAE1IS = 2, 255 ARM64_TLBI_ASIDE1IS = 3, 256 ARM64_TLBI_VAAE1IS = 4, 257 ARM64_TLBI_VALE1IS = 5, 258 ARM64_TLBI_VAALE1IS = 6, 259 ARM64_TLBI_ALLE2IS = 7, 260 ARM64_TLBI_VAE2IS = 8, 261 ARM64_TLBI_ALLE1IS = 9, 262 ARM64_TLBI_VALE2IS = 10, 263 ARM64_TLBI_VMALLS12E1IS = 11, 264 ARM64_TLBI_ALLE3IS = 12, 265 ARM64_TLBI_VAE3IS = 13, 266 ARM64_TLBI_VALE3IS = 14, 267 ARM64_TLBI_IPAS2E1IS = 15, 268 ARM64_TLBI_IPAS2LE1IS = 16, 269 ARM64_TLBI_IPAS2E1 = 17, 270 ARM64_TLBI_IPAS2LE1 = 18, 271 ARM64_TLBI_VMALLE1 = 19, 272 ARM64_TLBI_VAE1 = 20, 273 ARM64_TLBI_ASIDE1 = 21, 274 ARM64_TLBI_VAAE1 = 22, 275 ARM64_TLBI_VALE1 = 23, 276 ARM64_TLBI_VAALE1 = 24, 277 ARM64_TLBI_ALLE2 = 25, 278 ARM64_TLBI_VAE2 = 26, 279 ARM64_TLBI_ALLE1 = 27, 280 ARM64_TLBI_VALE2 = 28, 281 ARM64_TLBI_VMALLS12E1 = 29, 282 ARM64_TLBI_ALLE3 = 30, 283 ARM64_TLBI_VAE3 = 31, 284 ARM64_TLBI_VALE3 = 32 285 } 286 287 /// AT operations 288 enum arm64_at_op 289 { 290 ARM64_AT_S1E1R = 0, 291 ARM64_AT_S1E1W = 1, 292 ARM64_AT_S1E0R = 2, 293 ARM64_AT_S1E0W = 3, 294 ARM64_AT_S1E2R = 4, 295 ARM64_AT_S1E2W = 5, 296 ARM64_AT_S12E1R = 6, 297 ARM64_AT_S12E1W = 7, 298 ARM64_AT_S12E0R = 8, 299 ARM64_AT_S12E0W = 9, 300 ARM64_AT_S1E3R = 10, 301 ARM64_AT_S1E3W = 11 302 } 303 304 /// DC operations 305 enum arm64_dc_op 306 { 307 ARM64_DC_INVALID = 0, 308 ARM64_DC_ZVA = 1, 309 ARM64_DC_IVAC = 2, 310 ARM64_DC_ISW = 3, 311 ARM64_DC_CVAC = 4, 312 ARM64_DC_CSW = 5, 313 ARM64_DC_CVAU = 6, 314 ARM64_DC_CIVAC = 7, 315 ARM64_DC_CISW = 8 316 } 317 318 /// IC operations 319 enum arm64_ic_op 320 { 321 ARM64_IC_INVALID = 0, 322 ARM64_IC_IALLUIS = 1, 323 ARM64_IC_IALLU = 2, 324 ARM64_IC_IVAU = 3 325 } 326 327 /// Prefetch operations (PRFM) 328 enum arm64_prefetch_op 329 { 330 ARM64_PRFM_INVALID = 0, 331 ARM64_PRFM_PLDL1KEEP = 0x00 + 1, 332 ARM64_PRFM_PLDL1STRM = 0x01 + 1, 333 ARM64_PRFM_PLDL2KEEP = 0x02 + 1, 334 ARM64_PRFM_PLDL2STRM = 0x03 + 1, 335 ARM64_PRFM_PLDL3KEEP = 0x04 + 1, 336 ARM64_PRFM_PLDL3STRM = 0x05 + 1, 337 ARM64_PRFM_PLIL1KEEP = 0x08 + 1, 338 ARM64_PRFM_PLIL1STRM = 0x09 + 1, 339 ARM64_PRFM_PLIL2KEEP = 0x0a + 1, 340 ARM64_PRFM_PLIL2STRM = 0x0b + 1, 341 ARM64_PRFM_PLIL3KEEP = 0x0c + 1, 342 ARM64_PRFM_PLIL3STRM = 0x0d + 1, 343 ARM64_PRFM_PSTL1KEEP = 0x10 + 1, 344 ARM64_PRFM_PSTL1STRM = 0x11 + 1, 345 ARM64_PRFM_PSTL2KEEP = 0x12 + 1, 346 ARM64_PRFM_PSTL2STRM = 0x13 + 1, 347 ARM64_PRFM_PSTL3KEEP = 0x14 + 1, 348 ARM64_PRFM_PSTL3STRM = 0x15 + 1 349 } 350 351 /// ARM64 registers 352 enum arm64_reg 353 { 354 ARM64_REG_INVALID = 0, 355 356 ARM64_REG_X29 = 1, 357 ARM64_REG_X30 = 2, 358 ARM64_REG_NZCV = 3, 359 ARM64_REG_SP = 4, 360 ARM64_REG_WSP = 5, 361 ARM64_REG_WZR = 6, 362 ARM64_REG_XZR = 7, 363 ARM64_REG_B0 = 8, 364 ARM64_REG_B1 = 9, 365 ARM64_REG_B2 = 10, 366 ARM64_REG_B3 = 11, 367 ARM64_REG_B4 = 12, 368 ARM64_REG_B5 = 13, 369 ARM64_REG_B6 = 14, 370 ARM64_REG_B7 = 15, 371 ARM64_REG_B8 = 16, 372 ARM64_REG_B9 = 17, 373 ARM64_REG_B10 = 18, 374 ARM64_REG_B11 = 19, 375 ARM64_REG_B12 = 20, 376 ARM64_REG_B13 = 21, 377 ARM64_REG_B14 = 22, 378 ARM64_REG_B15 = 23, 379 ARM64_REG_B16 = 24, 380 ARM64_REG_B17 = 25, 381 ARM64_REG_B18 = 26, 382 ARM64_REG_B19 = 27, 383 ARM64_REG_B20 = 28, 384 ARM64_REG_B21 = 29, 385 ARM64_REG_B22 = 30, 386 ARM64_REG_B23 = 31, 387 ARM64_REG_B24 = 32, 388 ARM64_REG_B25 = 33, 389 ARM64_REG_B26 = 34, 390 ARM64_REG_B27 = 35, 391 ARM64_REG_B28 = 36, 392 ARM64_REG_B29 = 37, 393 ARM64_REG_B30 = 38, 394 ARM64_REG_B31 = 39, 395 ARM64_REG_D0 = 40, 396 ARM64_REG_D1 = 41, 397 ARM64_REG_D2 = 42, 398 ARM64_REG_D3 = 43, 399 ARM64_REG_D4 = 44, 400 ARM64_REG_D5 = 45, 401 ARM64_REG_D6 = 46, 402 ARM64_REG_D7 = 47, 403 ARM64_REG_D8 = 48, 404 ARM64_REG_D9 = 49, 405 ARM64_REG_D10 = 50, 406 ARM64_REG_D11 = 51, 407 ARM64_REG_D12 = 52, 408 ARM64_REG_D13 = 53, 409 ARM64_REG_D14 = 54, 410 ARM64_REG_D15 = 55, 411 ARM64_REG_D16 = 56, 412 ARM64_REG_D17 = 57, 413 ARM64_REG_D18 = 58, 414 ARM64_REG_D19 = 59, 415 ARM64_REG_D20 = 60, 416 ARM64_REG_D21 = 61, 417 ARM64_REG_D22 = 62, 418 ARM64_REG_D23 = 63, 419 ARM64_REG_D24 = 64, 420 ARM64_REG_D25 = 65, 421 ARM64_REG_D26 = 66, 422 ARM64_REG_D27 = 67, 423 ARM64_REG_D28 = 68, 424 ARM64_REG_D29 = 69, 425 ARM64_REG_D30 = 70, 426 ARM64_REG_D31 = 71, 427 ARM64_REG_H0 = 72, 428 ARM64_REG_H1 = 73, 429 ARM64_REG_H2 = 74, 430 ARM64_REG_H3 = 75, 431 ARM64_REG_H4 = 76, 432 ARM64_REG_H5 = 77, 433 ARM64_REG_H6 = 78, 434 ARM64_REG_H7 = 79, 435 ARM64_REG_H8 = 80, 436 ARM64_REG_H9 = 81, 437 ARM64_REG_H10 = 82, 438 ARM64_REG_H11 = 83, 439 ARM64_REG_H12 = 84, 440 ARM64_REG_H13 = 85, 441 ARM64_REG_H14 = 86, 442 ARM64_REG_H15 = 87, 443 ARM64_REG_H16 = 88, 444 ARM64_REG_H17 = 89, 445 ARM64_REG_H18 = 90, 446 ARM64_REG_H19 = 91, 447 ARM64_REG_H20 = 92, 448 ARM64_REG_H21 = 93, 449 ARM64_REG_H22 = 94, 450 ARM64_REG_H23 = 95, 451 ARM64_REG_H24 = 96, 452 ARM64_REG_H25 = 97, 453 ARM64_REG_H26 = 98, 454 ARM64_REG_H27 = 99, 455 ARM64_REG_H28 = 100, 456 ARM64_REG_H29 = 101, 457 ARM64_REG_H30 = 102, 458 ARM64_REG_H31 = 103, 459 ARM64_REG_Q0 = 104, 460 ARM64_REG_Q1 = 105, 461 ARM64_REG_Q2 = 106, 462 ARM64_REG_Q3 = 107, 463 ARM64_REG_Q4 = 108, 464 ARM64_REG_Q5 = 109, 465 ARM64_REG_Q6 = 110, 466 ARM64_REG_Q7 = 111, 467 ARM64_REG_Q8 = 112, 468 ARM64_REG_Q9 = 113, 469 ARM64_REG_Q10 = 114, 470 ARM64_REG_Q11 = 115, 471 ARM64_REG_Q12 = 116, 472 ARM64_REG_Q13 = 117, 473 ARM64_REG_Q14 = 118, 474 ARM64_REG_Q15 = 119, 475 ARM64_REG_Q16 = 120, 476 ARM64_REG_Q17 = 121, 477 ARM64_REG_Q18 = 122, 478 ARM64_REG_Q19 = 123, 479 ARM64_REG_Q20 = 124, 480 ARM64_REG_Q21 = 125, 481 ARM64_REG_Q22 = 126, 482 ARM64_REG_Q23 = 127, 483 ARM64_REG_Q24 = 128, 484 ARM64_REG_Q25 = 129, 485 ARM64_REG_Q26 = 130, 486 ARM64_REG_Q27 = 131, 487 ARM64_REG_Q28 = 132, 488 ARM64_REG_Q29 = 133, 489 ARM64_REG_Q30 = 134, 490 ARM64_REG_Q31 = 135, 491 ARM64_REG_S0 = 136, 492 ARM64_REG_S1 = 137, 493 ARM64_REG_S2 = 138, 494 ARM64_REG_S3 = 139, 495 ARM64_REG_S4 = 140, 496 ARM64_REG_S5 = 141, 497 ARM64_REG_S6 = 142, 498 ARM64_REG_S7 = 143, 499 ARM64_REG_S8 = 144, 500 ARM64_REG_S9 = 145, 501 ARM64_REG_S10 = 146, 502 ARM64_REG_S11 = 147, 503 ARM64_REG_S12 = 148, 504 ARM64_REG_S13 = 149, 505 ARM64_REG_S14 = 150, 506 ARM64_REG_S15 = 151, 507 ARM64_REG_S16 = 152, 508 ARM64_REG_S17 = 153, 509 ARM64_REG_S18 = 154, 510 ARM64_REG_S19 = 155, 511 ARM64_REG_S20 = 156, 512 ARM64_REG_S21 = 157, 513 ARM64_REG_S22 = 158, 514 ARM64_REG_S23 = 159, 515 ARM64_REG_S24 = 160, 516 ARM64_REG_S25 = 161, 517 ARM64_REG_S26 = 162, 518 ARM64_REG_S27 = 163, 519 ARM64_REG_S28 = 164, 520 ARM64_REG_S29 = 165, 521 ARM64_REG_S30 = 166, 522 ARM64_REG_S31 = 167, 523 ARM64_REG_W0 = 168, 524 ARM64_REG_W1 = 169, 525 ARM64_REG_W2 = 170, 526 ARM64_REG_W3 = 171, 527 ARM64_REG_W4 = 172, 528 ARM64_REG_W5 = 173, 529 ARM64_REG_W6 = 174, 530 ARM64_REG_W7 = 175, 531 ARM64_REG_W8 = 176, 532 ARM64_REG_W9 = 177, 533 ARM64_REG_W10 = 178, 534 ARM64_REG_W11 = 179, 535 ARM64_REG_W12 = 180, 536 ARM64_REG_W13 = 181, 537 ARM64_REG_W14 = 182, 538 ARM64_REG_W15 = 183, 539 ARM64_REG_W16 = 184, 540 ARM64_REG_W17 = 185, 541 ARM64_REG_W18 = 186, 542 ARM64_REG_W19 = 187, 543 ARM64_REG_W20 = 188, 544 ARM64_REG_W21 = 189, 545 ARM64_REG_W22 = 190, 546 ARM64_REG_W23 = 191, 547 ARM64_REG_W24 = 192, 548 ARM64_REG_W25 = 193, 549 ARM64_REG_W26 = 194, 550 ARM64_REG_W27 = 195, 551 ARM64_REG_W28 = 196, 552 ARM64_REG_W29 = 197, 553 ARM64_REG_W30 = 198, 554 ARM64_REG_X0 = 199, 555 ARM64_REG_X1 = 200, 556 ARM64_REG_X2 = 201, 557 ARM64_REG_X3 = 202, 558 ARM64_REG_X4 = 203, 559 ARM64_REG_X5 = 204, 560 ARM64_REG_X6 = 205, 561 ARM64_REG_X7 = 206, 562 ARM64_REG_X8 = 207, 563 ARM64_REG_X9 = 208, 564 ARM64_REG_X10 = 209, 565 ARM64_REG_X11 = 210, 566 ARM64_REG_X12 = 211, 567 ARM64_REG_X13 = 212, 568 ARM64_REG_X14 = 213, 569 ARM64_REG_X15 = 214, 570 ARM64_REG_X16 = 215, 571 ARM64_REG_X17 = 216, 572 ARM64_REG_X18 = 217, 573 ARM64_REG_X19 = 218, 574 ARM64_REG_X20 = 219, 575 ARM64_REG_X21 = 220, 576 ARM64_REG_X22 = 221, 577 ARM64_REG_X23 = 222, 578 ARM64_REG_X24 = 223, 579 ARM64_REG_X25 = 224, 580 ARM64_REG_X26 = 225, 581 ARM64_REG_X27 = 226, 582 ARM64_REG_X28 = 227, 583 584 ARM64_REG_V0 = 228, 585 ARM64_REG_V1 = 229, 586 ARM64_REG_V2 = 230, 587 ARM64_REG_V3 = 231, 588 ARM64_REG_V4 = 232, 589 ARM64_REG_V5 = 233, 590 ARM64_REG_V6 = 234, 591 ARM64_REG_V7 = 235, 592 ARM64_REG_V8 = 236, 593 ARM64_REG_V9 = 237, 594 ARM64_REG_V10 = 238, 595 ARM64_REG_V11 = 239, 596 ARM64_REG_V12 = 240, 597 ARM64_REG_V13 = 241, 598 ARM64_REG_V14 = 242, 599 ARM64_REG_V15 = 243, 600 ARM64_REG_V16 = 244, 601 ARM64_REG_V17 = 245, 602 ARM64_REG_V18 = 246, 603 ARM64_REG_V19 = 247, 604 ARM64_REG_V20 = 248, 605 ARM64_REG_V21 = 249, 606 ARM64_REG_V22 = 250, 607 ARM64_REG_V23 = 251, 608 ARM64_REG_V24 = 252, 609 ARM64_REG_V25 = 253, 610 ARM64_REG_V26 = 254, 611 ARM64_REG_V27 = 255, 612 ARM64_REG_V28 = 256, 613 ARM64_REG_V29 = 257, 614 ARM64_REG_V30 = 258, 615 ARM64_REG_V31 = 259, 616 617 ARM64_REG_ENDING = 260, // <-- mark the end of the list of registers 618 619 // alias registers 620 621 ARM64_REG_IP0 = ARM64_REG_X16, 622 ARM64_REG_IP1 = ARM64_REG_X17, 623 ARM64_REG_FP = ARM64_REG_X29, 624 ARM64_REG_LR = ARM64_REG_X30 625 } 626 627 /// Instruction's operand referring to memory 628 /// This is associated with ARM64_OP_MEM operand type above 629 struct arm64_op_mem 630 { 631 arm64_reg base; ///< base register 632 arm64_reg index; ///< index register 633 int disp; ///< displacement/offset value 634 } 635 636 /// Instruction operand 637 struct cs_arm64_op 638 { 639 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) 640 arm64_vas vas; ///< Vector Arrangement Specifier 641 arm64_vess vess; ///< Vector Element Size Specifier 642 643 ///< shifter type of this operand 644 ///< shifter value of this operand 645 struct _Anonymous_0 646 { 647 arm64_shifter type; 648 uint value; 649 } 650 651 _Anonymous_0 shift; 652 arm64_extender ext; ///< extender type of this operand 653 arm64_op_type type; ///< operand type 654 union 655 { 656 arm64_reg reg; ///< register value for REG operand 657 long imm; ///< immediate value, or index for C-IMM or IMM operand 658 double fp; ///< floating point value for FP operand 659 arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand 660 arm64_pstate pstate; ///< PState field of MSR instruction. 661 uint sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) 662 arm64_prefetch_op prefetch; ///< PRFM operation. 663 arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions). 664 } 665 666 /// How is this operand accessed? (READ, WRITE or READ|WRITE) 667 /// This field is combined of cs_ac_type. 668 /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 669 ubyte access; 670 } 671 672 /// Instruction structure 673 struct cs_arm64 674 { 675 arm64_cc cc; ///< conditional code for this insn 676 bool update_flags; ///< does this insn update flags? 677 bool writeback; ///< does this insn request writeback? 'True' means 'yes' 678 679 /// Number of operands of this instruction, 680 /// or 0 when instruction has no operand. 681 ubyte op_count; 682 683 cs_arm64_op[8] operands; ///< operands for this instruction. 684 } 685 686 /// ARM64 instruction 687 enum arm64_insn 688 { 689 ARM64_INS_INVALID = 0, 690 691 ARM64_INS_ABS = 1, 692 ARM64_INS_ADC = 2, 693 ARM64_INS_ADDHN = 3, 694 ARM64_INS_ADDHN2 = 4, 695 ARM64_INS_ADDP = 5, 696 ARM64_INS_ADD = 6, 697 ARM64_INS_ADDV = 7, 698 ARM64_INS_ADR = 8, 699 ARM64_INS_ADRP = 9, 700 ARM64_INS_AESD = 10, 701 ARM64_INS_AESE = 11, 702 ARM64_INS_AESIMC = 12, 703 ARM64_INS_AESMC = 13, 704 ARM64_INS_AND = 14, 705 ARM64_INS_ASR = 15, 706 ARM64_INS_B = 16, 707 ARM64_INS_BFM = 17, 708 ARM64_INS_BIC = 18, 709 ARM64_INS_BIF = 19, 710 ARM64_INS_BIT = 20, 711 ARM64_INS_BL = 21, 712 ARM64_INS_BLR = 22, 713 ARM64_INS_BR = 23, 714 ARM64_INS_BRK = 24, 715 ARM64_INS_BSL = 25, 716 ARM64_INS_CBNZ = 26, 717 ARM64_INS_CBZ = 27, 718 ARM64_INS_CCMN = 28, 719 ARM64_INS_CCMP = 29, 720 ARM64_INS_CLREX = 30, 721 ARM64_INS_CLS = 31, 722 ARM64_INS_CLZ = 32, 723 ARM64_INS_CMEQ = 33, 724 ARM64_INS_CMGE = 34, 725 ARM64_INS_CMGT = 35, 726 ARM64_INS_CMHI = 36, 727 ARM64_INS_CMHS = 37, 728 ARM64_INS_CMLE = 38, 729 ARM64_INS_CMLT = 39, 730 ARM64_INS_CMTST = 40, 731 ARM64_INS_CNT = 41, 732 ARM64_INS_MOV = 42, 733 ARM64_INS_CRC32B = 43, 734 ARM64_INS_CRC32CB = 44, 735 ARM64_INS_CRC32CH = 45, 736 ARM64_INS_CRC32CW = 46, 737 ARM64_INS_CRC32CX = 47, 738 ARM64_INS_CRC32H = 48, 739 ARM64_INS_CRC32W = 49, 740 ARM64_INS_CRC32X = 50, 741 ARM64_INS_CSEL = 51, 742 ARM64_INS_CSINC = 52, 743 ARM64_INS_CSINV = 53, 744 ARM64_INS_CSNEG = 54, 745 ARM64_INS_DCPS1 = 55, 746 ARM64_INS_DCPS2 = 56, 747 ARM64_INS_DCPS3 = 57, 748 ARM64_INS_DMB = 58, 749 ARM64_INS_DRPS = 59, 750 ARM64_INS_DSB = 60, 751 ARM64_INS_DUP = 61, 752 ARM64_INS_EON = 62, 753 ARM64_INS_EOR = 63, 754 ARM64_INS_ERET = 64, 755 ARM64_INS_EXTR = 65, 756 ARM64_INS_EXT = 66, 757 ARM64_INS_FABD = 67, 758 ARM64_INS_FABS = 68, 759 ARM64_INS_FACGE = 69, 760 ARM64_INS_FACGT = 70, 761 ARM64_INS_FADD = 71, 762 ARM64_INS_FADDP = 72, 763 ARM64_INS_FCCMP = 73, 764 ARM64_INS_FCCMPE = 74, 765 ARM64_INS_FCMEQ = 75, 766 ARM64_INS_FCMGE = 76, 767 ARM64_INS_FCMGT = 77, 768 ARM64_INS_FCMLE = 78, 769 ARM64_INS_FCMLT = 79, 770 ARM64_INS_FCMP = 80, 771 ARM64_INS_FCMPE = 81, 772 ARM64_INS_FCSEL = 82, 773 ARM64_INS_FCVTAS = 83, 774 ARM64_INS_FCVTAU = 84, 775 ARM64_INS_FCVT = 85, 776 ARM64_INS_FCVTL = 86, 777 ARM64_INS_FCVTL2 = 87, 778 ARM64_INS_FCVTMS = 88, 779 ARM64_INS_FCVTMU = 89, 780 ARM64_INS_FCVTNS = 90, 781 ARM64_INS_FCVTNU = 91, 782 ARM64_INS_FCVTN = 92, 783 ARM64_INS_FCVTN2 = 93, 784 ARM64_INS_FCVTPS = 94, 785 ARM64_INS_FCVTPU = 95, 786 ARM64_INS_FCVTXN = 96, 787 ARM64_INS_FCVTXN2 = 97, 788 ARM64_INS_FCVTZS = 98, 789 ARM64_INS_FCVTZU = 99, 790 ARM64_INS_FDIV = 100, 791 ARM64_INS_FMADD = 101, 792 ARM64_INS_FMAX = 102, 793 ARM64_INS_FMAXNM = 103, 794 ARM64_INS_FMAXNMP = 104, 795 ARM64_INS_FMAXNMV = 105, 796 ARM64_INS_FMAXP = 106, 797 ARM64_INS_FMAXV = 107, 798 ARM64_INS_FMIN = 108, 799 ARM64_INS_FMINNM = 109, 800 ARM64_INS_FMINNMP = 110, 801 ARM64_INS_FMINNMV = 111, 802 ARM64_INS_FMINP = 112, 803 ARM64_INS_FMINV = 113, 804 ARM64_INS_FMLA = 114, 805 ARM64_INS_FMLS = 115, 806 ARM64_INS_FMOV = 116, 807 ARM64_INS_FMSUB = 117, 808 ARM64_INS_FMUL = 118, 809 ARM64_INS_FMULX = 119, 810 ARM64_INS_FNEG = 120, 811 ARM64_INS_FNMADD = 121, 812 ARM64_INS_FNMSUB = 122, 813 ARM64_INS_FNMUL = 123, 814 ARM64_INS_FRECPE = 124, 815 ARM64_INS_FRECPS = 125, 816 ARM64_INS_FRECPX = 126, 817 ARM64_INS_FRINTA = 127, 818 ARM64_INS_FRINTI = 128, 819 ARM64_INS_FRINTM = 129, 820 ARM64_INS_FRINTN = 130, 821 ARM64_INS_FRINTP = 131, 822 ARM64_INS_FRINTX = 132, 823 ARM64_INS_FRINTZ = 133, 824 ARM64_INS_FRSQRTE = 134, 825 ARM64_INS_FRSQRTS = 135, 826 ARM64_INS_FSQRT = 136, 827 ARM64_INS_FSUB = 137, 828 ARM64_INS_HINT = 138, 829 ARM64_INS_HLT = 139, 830 ARM64_INS_HVC = 140, 831 ARM64_INS_INS = 141, 832 833 ARM64_INS_ISB = 142, 834 ARM64_INS_LD1 = 143, 835 ARM64_INS_LD1R = 144, 836 ARM64_INS_LD2R = 145, 837 ARM64_INS_LD2 = 146, 838 ARM64_INS_LD3R = 147, 839 ARM64_INS_LD3 = 148, 840 ARM64_INS_LD4 = 149, 841 ARM64_INS_LD4R = 150, 842 843 ARM64_INS_LDARB = 151, 844 ARM64_INS_LDARH = 152, 845 ARM64_INS_LDAR = 153, 846 ARM64_INS_LDAXP = 154, 847 ARM64_INS_LDAXRB = 155, 848 ARM64_INS_LDAXRH = 156, 849 ARM64_INS_LDAXR = 157, 850 ARM64_INS_LDNP = 158, 851 ARM64_INS_LDP = 159, 852 ARM64_INS_LDPSW = 160, 853 ARM64_INS_LDRB = 161, 854 ARM64_INS_LDR = 162, 855 ARM64_INS_LDRH = 163, 856 ARM64_INS_LDRSB = 164, 857 ARM64_INS_LDRSH = 165, 858 ARM64_INS_LDRSW = 166, 859 ARM64_INS_LDTRB = 167, 860 ARM64_INS_LDTRH = 168, 861 ARM64_INS_LDTRSB = 169, 862 863 ARM64_INS_LDTRSH = 170, 864 ARM64_INS_LDTRSW = 171, 865 ARM64_INS_LDTR = 172, 866 ARM64_INS_LDURB = 173, 867 ARM64_INS_LDUR = 174, 868 ARM64_INS_LDURH = 175, 869 ARM64_INS_LDURSB = 176, 870 ARM64_INS_LDURSH = 177, 871 ARM64_INS_LDURSW = 178, 872 ARM64_INS_LDXP = 179, 873 ARM64_INS_LDXRB = 180, 874 ARM64_INS_LDXRH = 181, 875 ARM64_INS_LDXR = 182, 876 ARM64_INS_LSL = 183, 877 ARM64_INS_LSR = 184, 878 ARM64_INS_MADD = 185, 879 ARM64_INS_MLA = 186, 880 ARM64_INS_MLS = 187, 881 ARM64_INS_MOVI = 188, 882 ARM64_INS_MOVK = 189, 883 ARM64_INS_MOVN = 190, 884 ARM64_INS_MOVZ = 191, 885 ARM64_INS_MRS = 192, 886 ARM64_INS_MSR = 193, 887 ARM64_INS_MSUB = 194, 888 ARM64_INS_MUL = 195, 889 ARM64_INS_MVNI = 196, 890 ARM64_INS_NEG = 197, 891 ARM64_INS_NOT = 198, 892 ARM64_INS_ORN = 199, 893 ARM64_INS_ORR = 200, 894 ARM64_INS_PMULL2 = 201, 895 ARM64_INS_PMULL = 202, 896 ARM64_INS_PMUL = 203, 897 ARM64_INS_PRFM = 204, 898 ARM64_INS_PRFUM = 205, 899 ARM64_INS_RADDHN = 206, 900 ARM64_INS_RADDHN2 = 207, 901 ARM64_INS_RBIT = 208, 902 ARM64_INS_RET = 209, 903 ARM64_INS_REV16 = 210, 904 ARM64_INS_REV32 = 211, 905 ARM64_INS_REV64 = 212, 906 ARM64_INS_REV = 213, 907 ARM64_INS_ROR = 214, 908 ARM64_INS_RSHRN2 = 215, 909 ARM64_INS_RSHRN = 216, 910 ARM64_INS_RSUBHN = 217, 911 ARM64_INS_RSUBHN2 = 218, 912 ARM64_INS_SABAL2 = 219, 913 ARM64_INS_SABAL = 220, 914 915 ARM64_INS_SABA = 221, 916 ARM64_INS_SABDL2 = 222, 917 ARM64_INS_SABDL = 223, 918 ARM64_INS_SABD = 224, 919 ARM64_INS_SADALP = 225, 920 ARM64_INS_SADDLP = 226, 921 ARM64_INS_SADDLV = 227, 922 ARM64_INS_SADDL2 = 228, 923 ARM64_INS_SADDL = 229, 924 ARM64_INS_SADDW2 = 230, 925 ARM64_INS_SADDW = 231, 926 ARM64_INS_SBC = 232, 927 ARM64_INS_SBFM = 233, 928 ARM64_INS_SCVTF = 234, 929 ARM64_INS_SDIV = 235, 930 ARM64_INS_SHA1C = 236, 931 ARM64_INS_SHA1H = 237, 932 ARM64_INS_SHA1M = 238, 933 ARM64_INS_SHA1P = 239, 934 ARM64_INS_SHA1SU0 = 240, 935 ARM64_INS_SHA1SU1 = 241, 936 ARM64_INS_SHA256H2 = 242, 937 ARM64_INS_SHA256H = 243, 938 ARM64_INS_SHA256SU0 = 244, 939 ARM64_INS_SHA256SU1 = 245, 940 ARM64_INS_SHADD = 246, 941 ARM64_INS_SHLL2 = 247, 942 ARM64_INS_SHLL = 248, 943 ARM64_INS_SHL = 249, 944 ARM64_INS_SHRN2 = 250, 945 ARM64_INS_SHRN = 251, 946 ARM64_INS_SHSUB = 252, 947 ARM64_INS_SLI = 253, 948 ARM64_INS_SMADDL = 254, 949 ARM64_INS_SMAXP = 255, 950 ARM64_INS_SMAXV = 256, 951 ARM64_INS_SMAX = 257, 952 ARM64_INS_SMC = 258, 953 ARM64_INS_SMINP = 259, 954 ARM64_INS_SMINV = 260, 955 ARM64_INS_SMIN = 261, 956 ARM64_INS_SMLAL2 = 262, 957 ARM64_INS_SMLAL = 263, 958 ARM64_INS_SMLSL2 = 264, 959 ARM64_INS_SMLSL = 265, 960 ARM64_INS_SMOV = 266, 961 ARM64_INS_SMSUBL = 267, 962 ARM64_INS_SMULH = 268, 963 ARM64_INS_SMULL2 = 269, 964 ARM64_INS_SMULL = 270, 965 ARM64_INS_SQABS = 271, 966 ARM64_INS_SQADD = 272, 967 ARM64_INS_SQDMLAL = 273, 968 ARM64_INS_SQDMLAL2 = 274, 969 ARM64_INS_SQDMLSL = 275, 970 ARM64_INS_SQDMLSL2 = 276, 971 ARM64_INS_SQDMULH = 277, 972 ARM64_INS_SQDMULL = 278, 973 ARM64_INS_SQDMULL2 = 279, 974 ARM64_INS_SQNEG = 280, 975 ARM64_INS_SQRDMULH = 281, 976 ARM64_INS_SQRSHL = 282, 977 ARM64_INS_SQRSHRN = 283, 978 ARM64_INS_SQRSHRN2 = 284, 979 ARM64_INS_SQRSHRUN = 285, 980 ARM64_INS_SQRSHRUN2 = 286, 981 ARM64_INS_SQSHLU = 287, 982 ARM64_INS_SQSHL = 288, 983 ARM64_INS_SQSHRN = 289, 984 ARM64_INS_SQSHRN2 = 290, 985 ARM64_INS_SQSHRUN = 291, 986 ARM64_INS_SQSHRUN2 = 292, 987 ARM64_INS_SQSUB = 293, 988 ARM64_INS_SQXTN2 = 294, 989 ARM64_INS_SQXTN = 295, 990 ARM64_INS_SQXTUN2 = 296, 991 ARM64_INS_SQXTUN = 297, 992 ARM64_INS_SRHADD = 298, 993 ARM64_INS_SRI = 299, 994 ARM64_INS_SRSHL = 300, 995 ARM64_INS_SRSHR = 301, 996 ARM64_INS_SRSRA = 302, 997 ARM64_INS_SSHLL2 = 303, 998 ARM64_INS_SSHLL = 304, 999 ARM64_INS_SSHL = 305, 1000 ARM64_INS_SSHR = 306, 1001 ARM64_INS_SSRA = 307, 1002 ARM64_INS_SSUBL2 = 308, 1003 ARM64_INS_SSUBL = 309, 1004 ARM64_INS_SSUBW2 = 310, 1005 ARM64_INS_SSUBW = 311, 1006 ARM64_INS_ST1 = 312, 1007 ARM64_INS_ST2 = 313, 1008 ARM64_INS_ST3 = 314, 1009 ARM64_INS_ST4 = 315, 1010 ARM64_INS_STLRB = 316, 1011 ARM64_INS_STLRH = 317, 1012 ARM64_INS_STLR = 318, 1013 ARM64_INS_STLXP = 319, 1014 ARM64_INS_STLXRB = 320, 1015 ARM64_INS_STLXRH = 321, 1016 ARM64_INS_STLXR = 322, 1017 ARM64_INS_STNP = 323, 1018 ARM64_INS_STP = 324, 1019 ARM64_INS_STRB = 325, 1020 ARM64_INS_STR = 326, 1021 ARM64_INS_STRH = 327, 1022 ARM64_INS_STTRB = 328, 1023 ARM64_INS_STTRH = 329, 1024 ARM64_INS_STTR = 330, 1025 ARM64_INS_STURB = 331, 1026 ARM64_INS_STUR = 332, 1027 ARM64_INS_STURH = 333, 1028 ARM64_INS_STXP = 334, 1029 ARM64_INS_STXRB = 335, 1030 ARM64_INS_STXRH = 336, 1031 ARM64_INS_STXR = 337, 1032 ARM64_INS_SUBHN = 338, 1033 ARM64_INS_SUBHN2 = 339, 1034 ARM64_INS_SUB = 340, 1035 ARM64_INS_SUQADD = 341, 1036 ARM64_INS_SVC = 342, 1037 ARM64_INS_SYSL = 343, 1038 ARM64_INS_SYS = 344, 1039 ARM64_INS_TBL = 345, 1040 ARM64_INS_TBNZ = 346, 1041 ARM64_INS_TBX = 347, 1042 ARM64_INS_TBZ = 348, 1043 ARM64_INS_TRN1 = 349, 1044 ARM64_INS_TRN2 = 350, 1045 ARM64_INS_UABAL2 = 351, 1046 ARM64_INS_UABAL = 352, 1047 ARM64_INS_UABA = 353, 1048 ARM64_INS_UABDL2 = 354, 1049 ARM64_INS_UABDL = 355, 1050 ARM64_INS_UABD = 356, 1051 ARM64_INS_UADALP = 357, 1052 ARM64_INS_UADDLP = 358, 1053 ARM64_INS_UADDLV = 359, 1054 ARM64_INS_UADDL2 = 360, 1055 ARM64_INS_UADDL = 361, 1056 ARM64_INS_UADDW2 = 362, 1057 ARM64_INS_UADDW = 363, 1058 ARM64_INS_UBFM = 364, 1059 ARM64_INS_UCVTF = 365, 1060 ARM64_INS_UDIV = 366, 1061 ARM64_INS_UHADD = 367, 1062 ARM64_INS_UHSUB = 368, 1063 ARM64_INS_UMADDL = 369, 1064 ARM64_INS_UMAXP = 370, 1065 ARM64_INS_UMAXV = 371, 1066 ARM64_INS_UMAX = 372, 1067 ARM64_INS_UMINP = 373, 1068 ARM64_INS_UMINV = 374, 1069 ARM64_INS_UMIN = 375, 1070 ARM64_INS_UMLAL2 = 376, 1071 ARM64_INS_UMLAL = 377, 1072 ARM64_INS_UMLSL2 = 378, 1073 ARM64_INS_UMLSL = 379, 1074 ARM64_INS_UMOV = 380, 1075 ARM64_INS_UMSUBL = 381, 1076 ARM64_INS_UMULH = 382, 1077 ARM64_INS_UMULL2 = 383, 1078 ARM64_INS_UMULL = 384, 1079 ARM64_INS_UQADD = 385, 1080 ARM64_INS_UQRSHL = 386, 1081 ARM64_INS_UQRSHRN = 387, 1082 ARM64_INS_UQRSHRN2 = 388, 1083 ARM64_INS_UQSHL = 389, 1084 ARM64_INS_UQSHRN = 390, 1085 ARM64_INS_UQSHRN2 = 391, 1086 ARM64_INS_UQSUB = 392, 1087 ARM64_INS_UQXTN2 = 393, 1088 ARM64_INS_UQXTN = 394, 1089 ARM64_INS_URECPE = 395, 1090 ARM64_INS_URHADD = 396, 1091 ARM64_INS_URSHL = 397, 1092 ARM64_INS_URSHR = 398, 1093 ARM64_INS_URSQRTE = 399, 1094 ARM64_INS_URSRA = 400, 1095 ARM64_INS_USHLL2 = 401, 1096 ARM64_INS_USHLL = 402, 1097 ARM64_INS_USHL = 403, 1098 ARM64_INS_USHR = 404, 1099 ARM64_INS_USQADD = 405, 1100 ARM64_INS_USRA = 406, 1101 ARM64_INS_USUBL2 = 407, 1102 ARM64_INS_USUBL = 408, 1103 ARM64_INS_USUBW2 = 409, 1104 ARM64_INS_USUBW = 410, 1105 ARM64_INS_UZP1 = 411, 1106 ARM64_INS_UZP2 = 412, 1107 ARM64_INS_XTN2 = 413, 1108 ARM64_INS_XTN = 414, 1109 ARM64_INS_ZIP1 = 415, 1110 ARM64_INS_ZIP2 = 416, 1111 1112 // alias insn 1113 ARM64_INS_MNEG = 417, 1114 ARM64_INS_UMNEGL = 418, 1115 ARM64_INS_SMNEGL = 419, 1116 ARM64_INS_NOP = 420, 1117 ARM64_INS_YIELD = 421, 1118 ARM64_INS_WFE = 422, 1119 ARM64_INS_WFI = 423, 1120 ARM64_INS_SEV = 424, 1121 ARM64_INS_SEVL = 425, 1122 ARM64_INS_NGC = 426, 1123 ARM64_INS_SBFIZ = 427, 1124 ARM64_INS_UBFIZ = 428, 1125 ARM64_INS_SBFX = 429, 1126 ARM64_INS_UBFX = 430, 1127 ARM64_INS_BFI = 431, 1128 ARM64_INS_BFXIL = 432, 1129 ARM64_INS_CMN = 433, 1130 ARM64_INS_MVN = 434, 1131 ARM64_INS_TST = 435, 1132 ARM64_INS_CSET = 436, 1133 ARM64_INS_CINC = 437, 1134 ARM64_INS_CSETM = 438, 1135 ARM64_INS_CINV = 439, 1136 ARM64_INS_CNEG = 440, 1137 ARM64_INS_SXTB = 441, 1138 ARM64_INS_SXTH = 442, 1139 ARM64_INS_SXTW = 443, 1140 ARM64_INS_CMP = 444, 1141 ARM64_INS_UXTB = 445, 1142 ARM64_INS_UXTH = 446, 1143 ARM64_INS_UXTW = 447, 1144 ARM64_INS_IC = 448, 1145 ARM64_INS_DC = 449, 1146 ARM64_INS_AT = 450, 1147 ARM64_INS_TLBI = 451, 1148 1149 ARM64_INS_NEGS = 452, 1150 ARM64_INS_NGCS = 453, 1151 1152 ARM64_INS_ENDING = 454 // <-- mark the end of the list of insn 1153 } 1154 1155 /// Group of ARM64 instructions 1156 enum arm64_insn_group 1157 { 1158 ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID 1159 1160 // Generic groups 1161 // all jump instructions (conditional+direct+indirect jumps) 1162 ARM64_GRP_JUMP = 1, ///< = CS_GRP_JUMP 1163 ARM64_GRP_CALL = 2, 1164 ARM64_GRP_RET = 3, 1165 ARM64_GRP_INT = 4, 1166 ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE 1167 ARM64_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE 1168 1169 // Architecture-specific groups 1170 ARM64_GRP_CRYPTO = 128, 1171 ARM64_GRP_FPARMV8 = 129, 1172 ARM64_GRP_NEON = 130, 1173 ARM64_GRP_CRC = 131, 1174 1175 ARM64_GRP_ENDING = 132 // <-- mark the end of the list of groups 1176 }