1 module capstone.arm; 2 3 extern (C): 4 5 /* Capstone Disassembly Engine */ 6 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 7 8 /// ARM shift type 9 enum arm_shifter 10 { 11 ARM_SFT_INVALID = 0, 12 ARM_SFT_ASR = 1, ///< shift with immediate const 13 ARM_SFT_LSL = 2, ///< shift with immediate const 14 ARM_SFT_LSR = 3, ///< shift with immediate const 15 ARM_SFT_ROR = 4, ///< shift with immediate const 16 ARM_SFT_RRX = 5, ///< shift with immediate const 17 ARM_SFT_ASR_REG = 6, ///< shift with register 18 ARM_SFT_LSL_REG = 7, ///< shift with register 19 ARM_SFT_LSR_REG = 8, ///< shift with register 20 ARM_SFT_ROR_REG = 9, ///< shift with register 21 ARM_SFT_RRX_REG = 10 ///< shift with register 22 } 23 24 /// ARM condition code 25 enum arm_cc 26 { 27 ARM_CC_INVALID = 0, 28 ARM_CC_EQ = 1, ///< Equal Equal 29 ARM_CC_NE = 2, ///< Not equal Not equal, or unordered 30 ARM_CC_HS = 3, ///< Carry set >, ==, or unordered 31 ARM_CC_LO = 4, ///< Carry clear Less than 32 ARM_CC_MI = 5, ///< Minus, negative Less than 33 ARM_CC_PL = 6, ///< Plus, positive or zero >, ==, or unordered 34 ARM_CC_VS = 7, ///< Overflow Unordered 35 ARM_CC_VC = 8, ///< No overflow Not unordered 36 ARM_CC_HI = 9, ///< Unsigned higher Greater than, or unordered 37 ARM_CC_LS = 10, ///< Unsigned lower or same Less than or equal 38 ARM_CC_GE = 11, ///< Greater than or equal Greater than or equal 39 ARM_CC_LT = 12, ///< Less than Less than, or unordered 40 ARM_CC_GT = 13, ///< Greater than Greater than 41 ARM_CC_LE = 14, ///< Less than or equal <, ==, or unordered 42 ARM_CC_AL = 15 ///< Always (unconditional) Always (unconditional) 43 } 44 45 enum arm_sysreg 46 { 47 /// Special registers for MSR 48 ARM_SYSREG_INVALID = 0, 49 50 // SPSR* registers can be OR combined 51 ARM_SYSREG_SPSR_C = 1, 52 ARM_SYSREG_SPSR_X = 2, 53 ARM_SYSREG_SPSR_S = 4, 54 ARM_SYSREG_SPSR_F = 8, 55 56 // CPSR* registers can be OR combined 57 ARM_SYSREG_CPSR_C = 16, 58 ARM_SYSREG_CPSR_X = 32, 59 ARM_SYSREG_CPSR_S = 64, 60 ARM_SYSREG_CPSR_F = 128, 61 62 // independent registers 63 ARM_SYSREG_APSR = 256, 64 ARM_SYSREG_APSR_G = 257, 65 ARM_SYSREG_APSR_NZCVQ = 258, 66 ARM_SYSREG_APSR_NZCVQG = 259, 67 68 ARM_SYSREG_IAPSR = 260, 69 ARM_SYSREG_IAPSR_G = 261, 70 ARM_SYSREG_IAPSR_NZCVQG = 262, 71 ARM_SYSREG_IAPSR_NZCVQ = 263, 72 73 ARM_SYSREG_EAPSR = 264, 74 ARM_SYSREG_EAPSR_G = 265, 75 ARM_SYSREG_EAPSR_NZCVQG = 266, 76 ARM_SYSREG_EAPSR_NZCVQ = 267, 77 78 ARM_SYSREG_XPSR = 268, 79 ARM_SYSREG_XPSR_G = 269, 80 ARM_SYSREG_XPSR_NZCVQG = 270, 81 ARM_SYSREG_XPSR_NZCVQ = 271, 82 83 ARM_SYSREG_IPSR = 272, 84 ARM_SYSREG_EPSR = 273, 85 ARM_SYSREG_IEPSR = 274, 86 87 ARM_SYSREG_MSP = 275, 88 ARM_SYSREG_PSP = 276, 89 ARM_SYSREG_PRIMASK = 277, 90 ARM_SYSREG_BASEPRI = 278, 91 ARM_SYSREG_BASEPRI_MAX = 279, 92 ARM_SYSREG_FAULTMASK = 280, 93 ARM_SYSREG_CONTROL = 281, 94 95 // Banked Registers 96 ARM_SYSREG_R8_USR = 282, 97 ARM_SYSREG_R9_USR = 283, 98 ARM_SYSREG_R10_USR = 284, 99 ARM_SYSREG_R11_USR = 285, 100 ARM_SYSREG_R12_USR = 286, 101 ARM_SYSREG_SP_USR = 287, 102 ARM_SYSREG_LR_USR = 288, 103 ARM_SYSREG_R8_FIQ = 289, 104 ARM_SYSREG_R9_FIQ = 290, 105 ARM_SYSREG_R10_FIQ = 291, 106 ARM_SYSREG_R11_FIQ = 292, 107 ARM_SYSREG_R12_FIQ = 293, 108 ARM_SYSREG_SP_FIQ = 294, 109 ARM_SYSREG_LR_FIQ = 295, 110 ARM_SYSREG_LR_IRQ = 296, 111 ARM_SYSREG_SP_IRQ = 297, 112 ARM_SYSREG_LR_SVC = 298, 113 ARM_SYSREG_SP_SVC = 299, 114 ARM_SYSREG_LR_ABT = 300, 115 ARM_SYSREG_SP_ABT = 301, 116 ARM_SYSREG_LR_UND = 302, 117 ARM_SYSREG_SP_UND = 303, 118 ARM_SYSREG_LR_MON = 304, 119 ARM_SYSREG_SP_MON = 305, 120 ARM_SYSREG_ELR_HYP = 306, 121 ARM_SYSREG_SP_HYP = 307, 122 123 ARM_SYSREG_SPSR_FIQ = 308, 124 ARM_SYSREG_SPSR_IRQ = 309, 125 ARM_SYSREG_SPSR_SVC = 310, 126 ARM_SYSREG_SPSR_ABT = 311, 127 ARM_SYSREG_SPSR_UND = 312, 128 ARM_SYSREG_SPSR_MON = 313, 129 ARM_SYSREG_SPSR_HYP = 314 130 } 131 132 /// The memory barrier constants map directly to the 4-bit encoding of 133 /// the option field for Memory Barrier operations. 134 enum arm_mem_barrier 135 { 136 ARM_MB_INVALID = 0, 137 ARM_MB_RESERVED_0 = 1, 138 ARM_MB_OSHLD = 2, 139 ARM_MB_OSHST = 3, 140 ARM_MB_OSH = 4, 141 ARM_MB_RESERVED_4 = 5, 142 ARM_MB_NSHLD = 6, 143 ARM_MB_NSHST = 7, 144 ARM_MB_NSH = 8, 145 ARM_MB_RESERVED_8 = 9, 146 ARM_MB_ISHLD = 10, 147 ARM_MB_ISHST = 11, 148 ARM_MB_ISH = 12, 149 ARM_MB_RESERVED_12 = 13, 150 ARM_MB_LD = 14, 151 ARM_MB_ST = 15, 152 ARM_MB_SY = 16 153 } 154 155 /// Operand type for instruction's operands 156 enum arm_op_type 157 { 158 ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 159 ARM_OP_REG = 1, ///< = CS_OP_REG (Register operand). 160 ARM_OP_IMM = 2, ///< = CS_OP_IMM (Immediate operand). 161 ARM_OP_MEM = 3, ///< = CS_OP_MEM (Memory operand). 162 ARM_OP_FP = 4, ///< = CS_OP_FP (Floating-Point operand). 163 ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers) 164 ARM_OP_PIMM = 65, ///< P-Immediate (coprocessor registers) 165 ARM_OP_SETEND = 66, ///< operand for SETEND instruction 166 ARM_OP_SYSREG = 67 ///< MSR/MRS special register operand 167 } 168 169 /// Operand type for SETEND instruction 170 enum arm_setend_type 171 { 172 ARM_SETEND_INVALID = 0, ///< Uninitialized. 173 ARM_SETEND_BE = 1, ///< BE operand. 174 ARM_SETEND_LE = 2 ///< LE operand 175 } 176 177 enum arm_cpsmode_type 178 { 179 ARM_CPSMODE_INVALID = 0, 180 ARM_CPSMODE_IE = 2, 181 ARM_CPSMODE_ID = 3 182 } 183 184 /// Operand type for SETEND instruction 185 enum arm_cpsflag_type 186 { 187 ARM_CPSFLAG_INVALID = 0, 188 ARM_CPSFLAG_F = 1, 189 ARM_CPSFLAG_I = 2, 190 ARM_CPSFLAG_A = 4, 191 ARM_CPSFLAG_NONE = 16 ///< no flag 192 } 193 194 /// Data type for elements of vector instructions. 195 enum arm_vectordata_type 196 { 197 ARM_VECTORDATA_INVALID = 0, 198 199 // Integer type 200 ARM_VECTORDATA_I8 = 1, 201 ARM_VECTORDATA_I16 = 2, 202 ARM_VECTORDATA_I32 = 3, 203 ARM_VECTORDATA_I64 = 4, 204 205 // Signed integer type 206 ARM_VECTORDATA_S8 = 5, 207 ARM_VECTORDATA_S16 = 6, 208 ARM_VECTORDATA_S32 = 7, 209 ARM_VECTORDATA_S64 = 8, 210 211 // Unsigned integer type 212 ARM_VECTORDATA_U8 = 9, 213 ARM_VECTORDATA_U16 = 10, 214 ARM_VECTORDATA_U32 = 11, 215 ARM_VECTORDATA_U64 = 12, 216 217 // Data type for VMUL/VMULL 218 ARM_VECTORDATA_P8 = 13, 219 220 // Floating type 221 ARM_VECTORDATA_F32 = 14, 222 ARM_VECTORDATA_F64 = 15, 223 224 // Convert float <-> float 225 ARM_VECTORDATA_F16F64 = 16, // f16.f64 226 ARM_VECTORDATA_F64F16 = 17, // f64.f16 227 ARM_VECTORDATA_F32F16 = 18, // f32.f16 228 ARM_VECTORDATA_F16F32 = 19, // f32.f16 229 ARM_VECTORDATA_F64F32 = 20, // f64.f32 230 ARM_VECTORDATA_F32F64 = 21, // f32.f64 231 232 // Convert integer <-> float 233 ARM_VECTORDATA_S32F32 = 22, // s32.f32 234 ARM_VECTORDATA_U32F32 = 23, // u32.f32 235 ARM_VECTORDATA_F32S32 = 24, // f32.s32 236 ARM_VECTORDATA_F32U32 = 25, // f32.u32 237 ARM_VECTORDATA_F64S16 = 26, // f64.s16 238 ARM_VECTORDATA_F32S16 = 27, // f32.s16 239 ARM_VECTORDATA_F64S32 = 28, // f64.s32 240 ARM_VECTORDATA_S16F64 = 29, // s16.f64 241 ARM_VECTORDATA_S16F32 = 30, // s16.f64 242 ARM_VECTORDATA_S32F64 = 31, // s32.f64 243 ARM_VECTORDATA_U16F64 = 32, // u16.f64 244 ARM_VECTORDATA_U16F32 = 33, // u16.f32 245 ARM_VECTORDATA_U32F64 = 34, // u32.f64 246 ARM_VECTORDATA_F64U16 = 35, // f64.u16 247 ARM_VECTORDATA_F32U16 = 36, // f32.u16 248 ARM_VECTORDATA_F64U32 = 37 // f64.u32 249 } 250 251 /// ARM registers 252 enum arm_reg 253 { 254 ARM_REG_INVALID = 0, 255 ARM_REG_APSR = 1, 256 ARM_REG_APSR_NZCV = 2, 257 ARM_REG_CPSR = 3, 258 ARM_REG_FPEXC = 4, 259 ARM_REG_FPINST = 5, 260 ARM_REG_FPSCR = 6, 261 ARM_REG_FPSCR_NZCV = 7, 262 ARM_REG_FPSID = 8, 263 ARM_REG_ITSTATE = 9, 264 ARM_REG_LR = 10, 265 ARM_REG_PC = 11, 266 ARM_REG_SP = 12, 267 ARM_REG_SPSR = 13, 268 ARM_REG_D0 = 14, 269 ARM_REG_D1 = 15, 270 ARM_REG_D2 = 16, 271 ARM_REG_D3 = 17, 272 ARM_REG_D4 = 18, 273 ARM_REG_D5 = 19, 274 ARM_REG_D6 = 20, 275 ARM_REG_D7 = 21, 276 ARM_REG_D8 = 22, 277 ARM_REG_D9 = 23, 278 ARM_REG_D10 = 24, 279 ARM_REG_D11 = 25, 280 ARM_REG_D12 = 26, 281 ARM_REG_D13 = 27, 282 ARM_REG_D14 = 28, 283 ARM_REG_D15 = 29, 284 ARM_REG_D16 = 30, 285 ARM_REG_D17 = 31, 286 ARM_REG_D18 = 32, 287 ARM_REG_D19 = 33, 288 ARM_REG_D20 = 34, 289 ARM_REG_D21 = 35, 290 ARM_REG_D22 = 36, 291 ARM_REG_D23 = 37, 292 ARM_REG_D24 = 38, 293 ARM_REG_D25 = 39, 294 ARM_REG_D26 = 40, 295 ARM_REG_D27 = 41, 296 ARM_REG_D28 = 42, 297 ARM_REG_D29 = 43, 298 ARM_REG_D30 = 44, 299 ARM_REG_D31 = 45, 300 ARM_REG_FPINST2 = 46, 301 ARM_REG_MVFR0 = 47, 302 ARM_REG_MVFR1 = 48, 303 ARM_REG_MVFR2 = 49, 304 ARM_REG_Q0 = 50, 305 ARM_REG_Q1 = 51, 306 ARM_REG_Q2 = 52, 307 ARM_REG_Q3 = 53, 308 ARM_REG_Q4 = 54, 309 ARM_REG_Q5 = 55, 310 ARM_REG_Q6 = 56, 311 ARM_REG_Q7 = 57, 312 ARM_REG_Q8 = 58, 313 ARM_REG_Q9 = 59, 314 ARM_REG_Q10 = 60, 315 ARM_REG_Q11 = 61, 316 ARM_REG_Q12 = 62, 317 ARM_REG_Q13 = 63, 318 ARM_REG_Q14 = 64, 319 ARM_REG_Q15 = 65, 320 ARM_REG_R0 = 66, 321 ARM_REG_R1 = 67, 322 ARM_REG_R2 = 68, 323 ARM_REG_R3 = 69, 324 ARM_REG_R4 = 70, 325 ARM_REG_R5 = 71, 326 ARM_REG_R6 = 72, 327 ARM_REG_R7 = 73, 328 ARM_REG_R8 = 74, 329 ARM_REG_R9 = 75, 330 ARM_REG_R10 = 76, 331 ARM_REG_R11 = 77, 332 ARM_REG_R12 = 78, 333 ARM_REG_S0 = 79, 334 ARM_REG_S1 = 80, 335 ARM_REG_S2 = 81, 336 ARM_REG_S3 = 82, 337 ARM_REG_S4 = 83, 338 ARM_REG_S5 = 84, 339 ARM_REG_S6 = 85, 340 ARM_REG_S7 = 86, 341 ARM_REG_S8 = 87, 342 ARM_REG_S9 = 88, 343 ARM_REG_S10 = 89, 344 ARM_REG_S11 = 90, 345 ARM_REG_S12 = 91, 346 ARM_REG_S13 = 92, 347 ARM_REG_S14 = 93, 348 ARM_REG_S15 = 94, 349 ARM_REG_S16 = 95, 350 ARM_REG_S17 = 96, 351 ARM_REG_S18 = 97, 352 ARM_REG_S19 = 98, 353 ARM_REG_S20 = 99, 354 ARM_REG_S21 = 100, 355 ARM_REG_S22 = 101, 356 ARM_REG_S23 = 102, 357 ARM_REG_S24 = 103, 358 ARM_REG_S25 = 104, 359 ARM_REG_S26 = 105, 360 ARM_REG_S27 = 106, 361 ARM_REG_S28 = 107, 362 ARM_REG_S29 = 108, 363 ARM_REG_S30 = 109, 364 ARM_REG_S31 = 110, 365 366 ARM_REG_ENDING = 111, // <-- mark the end of the list or registers 367 368 // alias registers 369 ARM_REG_R13 = ARM_REG_SP, 370 ARM_REG_R14 = ARM_REG_LR, 371 ARM_REG_R15 = ARM_REG_PC, 372 373 ARM_REG_SB = ARM_REG_R9, 374 ARM_REG_SL = ARM_REG_R10, 375 ARM_REG_FP = ARM_REG_R11, 376 ARM_REG_IP = ARM_REG_R12 377 } 378 379 /// Instruction's operand referring to memory 380 /// This is associated with ARM_OP_MEM operand type above 381 struct arm_op_mem 382 { 383 arm_reg base; ///< base register 384 arm_reg index; ///< index register 385 int scale; ///< scale for index register (can be 1, or -1) 386 int disp; ///< displacement/offset value 387 int lshift; ///< left-shift on index register, or 0 if irrelevant. 388 } 389 390 /// Instruction operand 391 struct cs_arm_op 392 { 393 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) 394 395 struct _Anonymous_0 396 { 397 arm_shifter type; 398 uint value; 399 } 400 401 _Anonymous_0 shift; 402 403 arm_op_type type; ///< operand type 404 405 union 406 { 407 int reg; ///< register value for REG/SYSREG operand 408 int imm; ///< immediate value for C-IMM, P-IMM or IMM operand 409 double fp; ///< floating point value for FP operand 410 arm_op_mem mem; ///< base/index/scale/disp value for MEM operand 411 arm_setend_type setend; ///< SETEND instruction's operand type 412 } 413 414 /// in some instructions, an operand can be subtracted or added to 415 /// the base register, 416 /// if TRUE, this operand is subtracted. otherwise, it is added. 417 bool subtracted; 418 419 /// How is this operand accessed? (READ, WRITE or READ|WRITE) 420 /// This field is combined of cs_ac_type. 421 /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 422 ubyte access; 423 424 /// Neon lane index for NEON instructions (or -1 if irrelevant) 425 byte neon_lane; 426 } 427 428 /// Instruction structure 429 struct cs_arm 430 { 431 bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions) 432 int vector_size; ///< Scalar size for vector instructions 433 arm_vectordata_type vector_data; ///< Data type for elements of vector instructions 434 arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction 435 arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction 436 arm_cc cc; ///< conditional code for this insn 437 bool update_flags; ///< does this insn update flags? 438 bool writeback; ///< does this insn write-back? 439 arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions 440 441 /// Number of operands of this instruction, 442 /// or 0 when instruction has no operand. 443 ubyte op_count; 444 445 cs_arm_op[36] operands; ///< operands for this instruction. 446 } 447 448 /// ARM instruction 449 enum arm_insn 450 { 451 ARM_INS_INVALID = 0, 452 453 ARM_INS_ADC = 1, 454 ARM_INS_ADD = 2, 455 ARM_INS_ADR = 3, 456 ARM_INS_AESD = 4, 457 ARM_INS_AESE = 5, 458 ARM_INS_AESIMC = 6, 459 ARM_INS_AESMC = 7, 460 ARM_INS_AND = 8, 461 ARM_INS_BFC = 9, 462 ARM_INS_BFI = 10, 463 ARM_INS_BIC = 11, 464 ARM_INS_BKPT = 12, 465 ARM_INS_BL = 13, 466 ARM_INS_BLX = 14, 467 ARM_INS_BX = 15, 468 ARM_INS_BXJ = 16, 469 ARM_INS_B = 17, 470 ARM_INS_CDP = 18, 471 ARM_INS_CDP2 = 19, 472 ARM_INS_CLREX = 20, 473 ARM_INS_CLZ = 21, 474 ARM_INS_CMN = 22, 475 ARM_INS_CMP = 23, 476 ARM_INS_CPS = 24, 477 ARM_INS_CRC32B = 25, 478 ARM_INS_CRC32CB = 26, 479 ARM_INS_CRC32CH = 27, 480 ARM_INS_CRC32CW = 28, 481 ARM_INS_CRC32H = 29, 482 ARM_INS_CRC32W = 30, 483 ARM_INS_DBG = 31, 484 ARM_INS_DMB = 32, 485 ARM_INS_DSB = 33, 486 ARM_INS_EOR = 34, 487 ARM_INS_ERET = 35, 488 ARM_INS_VMOV = 36, 489 ARM_INS_FLDMDBX = 37, 490 ARM_INS_FLDMIAX = 38, 491 ARM_INS_VMRS = 39, 492 ARM_INS_FSTMDBX = 40, 493 ARM_INS_FSTMIAX = 41, 494 ARM_INS_HINT = 42, 495 ARM_INS_HLT = 43, 496 ARM_INS_HVC = 44, 497 ARM_INS_ISB = 45, 498 ARM_INS_LDA = 46, 499 ARM_INS_LDAB = 47, 500 ARM_INS_LDAEX = 48, 501 ARM_INS_LDAEXB = 49, 502 ARM_INS_LDAEXD = 50, 503 ARM_INS_LDAEXH = 51, 504 ARM_INS_LDAH = 52, 505 ARM_INS_LDC2L = 53, 506 ARM_INS_LDC2 = 54, 507 ARM_INS_LDCL = 55, 508 ARM_INS_LDC = 56, 509 ARM_INS_LDMDA = 57, 510 ARM_INS_LDMDB = 58, 511 ARM_INS_LDM = 59, 512 ARM_INS_LDMIB = 60, 513 ARM_INS_LDRBT = 61, 514 ARM_INS_LDRB = 62, 515 ARM_INS_LDRD = 63, 516 ARM_INS_LDREX = 64, 517 ARM_INS_LDREXB = 65, 518 ARM_INS_LDREXD = 66, 519 ARM_INS_LDREXH = 67, 520 ARM_INS_LDRH = 68, 521 ARM_INS_LDRHT = 69, 522 ARM_INS_LDRSB = 70, 523 ARM_INS_LDRSBT = 71, 524 ARM_INS_LDRSH = 72, 525 ARM_INS_LDRSHT = 73, 526 ARM_INS_LDRT = 74, 527 ARM_INS_LDR = 75, 528 ARM_INS_MCR = 76, 529 ARM_INS_MCR2 = 77, 530 ARM_INS_MCRR = 78, 531 ARM_INS_MCRR2 = 79, 532 ARM_INS_MLA = 80, 533 ARM_INS_MLS = 81, 534 ARM_INS_MOV = 82, 535 ARM_INS_MOVT = 83, 536 ARM_INS_MOVW = 84, 537 ARM_INS_MRC = 85, 538 ARM_INS_MRC2 = 86, 539 ARM_INS_MRRC = 87, 540 ARM_INS_MRRC2 = 88, 541 ARM_INS_MRS = 89, 542 ARM_INS_MSR = 90, 543 ARM_INS_MUL = 91, 544 ARM_INS_MVN = 92, 545 ARM_INS_ORR = 93, 546 ARM_INS_PKHBT = 94, 547 ARM_INS_PKHTB = 95, 548 ARM_INS_PLDW = 96, 549 ARM_INS_PLD = 97, 550 ARM_INS_PLI = 98, 551 ARM_INS_QADD = 99, 552 ARM_INS_QADD16 = 100, 553 ARM_INS_QADD8 = 101, 554 ARM_INS_QASX = 102, 555 ARM_INS_QDADD = 103, 556 ARM_INS_QDSUB = 104, 557 ARM_INS_QSAX = 105, 558 ARM_INS_QSUB = 106, 559 ARM_INS_QSUB16 = 107, 560 ARM_INS_QSUB8 = 108, 561 ARM_INS_RBIT = 109, 562 ARM_INS_REV = 110, 563 ARM_INS_REV16 = 111, 564 ARM_INS_REVSH = 112, 565 ARM_INS_RFEDA = 113, 566 ARM_INS_RFEDB = 114, 567 ARM_INS_RFEIA = 115, 568 ARM_INS_RFEIB = 116, 569 ARM_INS_RSB = 117, 570 ARM_INS_RSC = 118, 571 ARM_INS_SADD16 = 119, 572 ARM_INS_SADD8 = 120, 573 ARM_INS_SASX = 121, 574 ARM_INS_SBC = 122, 575 ARM_INS_SBFX = 123, 576 ARM_INS_SDIV = 124, 577 ARM_INS_SEL = 125, 578 ARM_INS_SETEND = 126, 579 ARM_INS_SHA1C = 127, 580 ARM_INS_SHA1H = 128, 581 ARM_INS_SHA1M = 129, 582 ARM_INS_SHA1P = 130, 583 ARM_INS_SHA1SU0 = 131, 584 ARM_INS_SHA1SU1 = 132, 585 ARM_INS_SHA256H = 133, 586 ARM_INS_SHA256H2 = 134, 587 ARM_INS_SHA256SU0 = 135, 588 ARM_INS_SHA256SU1 = 136, 589 ARM_INS_SHADD16 = 137, 590 ARM_INS_SHADD8 = 138, 591 ARM_INS_SHASX = 139, 592 ARM_INS_SHSAX = 140, 593 ARM_INS_SHSUB16 = 141, 594 ARM_INS_SHSUB8 = 142, 595 ARM_INS_SMC = 143, 596 ARM_INS_SMLABB = 144, 597 ARM_INS_SMLABT = 145, 598 ARM_INS_SMLAD = 146, 599 ARM_INS_SMLADX = 147, 600 ARM_INS_SMLAL = 148, 601 ARM_INS_SMLALBB = 149, 602 ARM_INS_SMLALBT = 150, 603 ARM_INS_SMLALD = 151, 604 ARM_INS_SMLALDX = 152, 605 ARM_INS_SMLALTB = 153, 606 ARM_INS_SMLALTT = 154, 607 ARM_INS_SMLATB = 155, 608 ARM_INS_SMLATT = 156, 609 ARM_INS_SMLAWB = 157, 610 ARM_INS_SMLAWT = 158, 611 ARM_INS_SMLSD = 159, 612 ARM_INS_SMLSDX = 160, 613 ARM_INS_SMLSLD = 161, 614 ARM_INS_SMLSLDX = 162, 615 ARM_INS_SMMLA = 163, 616 ARM_INS_SMMLAR = 164, 617 ARM_INS_SMMLS = 165, 618 ARM_INS_SMMLSR = 166, 619 ARM_INS_SMMUL = 167, 620 ARM_INS_SMMULR = 168, 621 ARM_INS_SMUAD = 169, 622 ARM_INS_SMUADX = 170, 623 ARM_INS_SMULBB = 171, 624 ARM_INS_SMULBT = 172, 625 ARM_INS_SMULL = 173, 626 ARM_INS_SMULTB = 174, 627 ARM_INS_SMULTT = 175, 628 ARM_INS_SMULWB = 176, 629 ARM_INS_SMULWT = 177, 630 ARM_INS_SMUSD = 178, 631 ARM_INS_SMUSDX = 179, 632 ARM_INS_SRSDA = 180, 633 ARM_INS_SRSDB = 181, 634 ARM_INS_SRSIA = 182, 635 ARM_INS_SRSIB = 183, 636 ARM_INS_SSAT = 184, 637 ARM_INS_SSAT16 = 185, 638 ARM_INS_SSAX = 186, 639 ARM_INS_SSUB16 = 187, 640 ARM_INS_SSUB8 = 188, 641 ARM_INS_STC2L = 189, 642 ARM_INS_STC2 = 190, 643 ARM_INS_STCL = 191, 644 ARM_INS_STC = 192, 645 ARM_INS_STL = 193, 646 ARM_INS_STLB = 194, 647 ARM_INS_STLEX = 195, 648 ARM_INS_STLEXB = 196, 649 ARM_INS_STLEXD = 197, 650 ARM_INS_STLEXH = 198, 651 ARM_INS_STLH = 199, 652 ARM_INS_STMDA = 200, 653 ARM_INS_STMDB = 201, 654 ARM_INS_STM = 202, 655 ARM_INS_STMIB = 203, 656 ARM_INS_STRBT = 204, 657 ARM_INS_STRB = 205, 658 ARM_INS_STRD = 206, 659 ARM_INS_STREX = 207, 660 ARM_INS_STREXB = 208, 661 ARM_INS_STREXD = 209, 662 ARM_INS_STREXH = 210, 663 ARM_INS_STRH = 211, 664 ARM_INS_STRHT = 212, 665 ARM_INS_STRT = 213, 666 ARM_INS_STR = 214, 667 ARM_INS_SUB = 215, 668 ARM_INS_SVC = 216, 669 ARM_INS_SWP = 217, 670 ARM_INS_SWPB = 218, 671 ARM_INS_SXTAB = 219, 672 ARM_INS_SXTAB16 = 220, 673 ARM_INS_SXTAH = 221, 674 ARM_INS_SXTB = 222, 675 ARM_INS_SXTB16 = 223, 676 ARM_INS_SXTH = 224, 677 ARM_INS_TEQ = 225, 678 ARM_INS_TRAP = 226, 679 ARM_INS_TST = 227, 680 ARM_INS_UADD16 = 228, 681 ARM_INS_UADD8 = 229, 682 ARM_INS_UASX = 230, 683 ARM_INS_UBFX = 231, 684 ARM_INS_UDF = 232, 685 ARM_INS_UDIV = 233, 686 ARM_INS_UHADD16 = 234, 687 ARM_INS_UHADD8 = 235, 688 ARM_INS_UHASX = 236, 689 ARM_INS_UHSAX = 237, 690 ARM_INS_UHSUB16 = 238, 691 ARM_INS_UHSUB8 = 239, 692 ARM_INS_UMAAL = 240, 693 ARM_INS_UMLAL = 241, 694 ARM_INS_UMULL = 242, 695 ARM_INS_UQADD16 = 243, 696 ARM_INS_UQADD8 = 244, 697 ARM_INS_UQASX = 245, 698 ARM_INS_UQSAX = 246, 699 ARM_INS_UQSUB16 = 247, 700 ARM_INS_UQSUB8 = 248, 701 ARM_INS_USAD8 = 249, 702 ARM_INS_USADA8 = 250, 703 ARM_INS_USAT = 251, 704 ARM_INS_USAT16 = 252, 705 ARM_INS_USAX = 253, 706 ARM_INS_USUB16 = 254, 707 ARM_INS_USUB8 = 255, 708 ARM_INS_UXTAB = 256, 709 ARM_INS_UXTAB16 = 257, 710 ARM_INS_UXTAH = 258, 711 ARM_INS_UXTB = 259, 712 ARM_INS_UXTB16 = 260, 713 ARM_INS_UXTH = 261, 714 ARM_INS_VABAL = 262, 715 ARM_INS_VABA = 263, 716 ARM_INS_VABDL = 264, 717 ARM_INS_VABD = 265, 718 ARM_INS_VABS = 266, 719 ARM_INS_VACGE = 267, 720 ARM_INS_VACGT = 268, 721 ARM_INS_VADD = 269, 722 ARM_INS_VADDHN = 270, 723 ARM_INS_VADDL = 271, 724 ARM_INS_VADDW = 272, 725 ARM_INS_VAND = 273, 726 ARM_INS_VBIC = 274, 727 ARM_INS_VBIF = 275, 728 ARM_INS_VBIT = 276, 729 ARM_INS_VBSL = 277, 730 ARM_INS_VCEQ = 278, 731 ARM_INS_VCGE = 279, 732 ARM_INS_VCGT = 280, 733 ARM_INS_VCLE = 281, 734 ARM_INS_VCLS = 282, 735 ARM_INS_VCLT = 283, 736 ARM_INS_VCLZ = 284, 737 ARM_INS_VCMP = 285, 738 ARM_INS_VCMPE = 286, 739 ARM_INS_VCNT = 287, 740 ARM_INS_VCVTA = 288, 741 ARM_INS_VCVTB = 289, 742 ARM_INS_VCVT = 290, 743 ARM_INS_VCVTM = 291, 744 ARM_INS_VCVTN = 292, 745 ARM_INS_VCVTP = 293, 746 ARM_INS_VCVTT = 294, 747 ARM_INS_VDIV = 295, 748 ARM_INS_VDUP = 296, 749 ARM_INS_VEOR = 297, 750 ARM_INS_VEXT = 298, 751 ARM_INS_VFMA = 299, 752 ARM_INS_VFMS = 300, 753 ARM_INS_VFNMA = 301, 754 ARM_INS_VFNMS = 302, 755 ARM_INS_VHADD = 303, 756 ARM_INS_VHSUB = 304, 757 ARM_INS_VLD1 = 305, 758 ARM_INS_VLD2 = 306, 759 ARM_INS_VLD3 = 307, 760 ARM_INS_VLD4 = 308, 761 ARM_INS_VLDMDB = 309, 762 ARM_INS_VLDMIA = 310, 763 ARM_INS_VLDR = 311, 764 ARM_INS_VMAXNM = 312, 765 ARM_INS_VMAX = 313, 766 ARM_INS_VMINNM = 314, 767 ARM_INS_VMIN = 315, 768 ARM_INS_VMLA = 316, 769 ARM_INS_VMLAL = 317, 770 ARM_INS_VMLS = 318, 771 ARM_INS_VMLSL = 319, 772 ARM_INS_VMOVL = 320, 773 ARM_INS_VMOVN = 321, 774 ARM_INS_VMSR = 322, 775 ARM_INS_VMUL = 323, 776 ARM_INS_VMULL = 324, 777 ARM_INS_VMVN = 325, 778 ARM_INS_VNEG = 326, 779 ARM_INS_VNMLA = 327, 780 ARM_INS_VNMLS = 328, 781 ARM_INS_VNMUL = 329, 782 ARM_INS_VORN = 330, 783 ARM_INS_VORR = 331, 784 ARM_INS_VPADAL = 332, 785 ARM_INS_VPADDL = 333, 786 ARM_INS_VPADD = 334, 787 ARM_INS_VPMAX = 335, 788 ARM_INS_VPMIN = 336, 789 ARM_INS_VQABS = 337, 790 ARM_INS_VQADD = 338, 791 ARM_INS_VQDMLAL = 339, 792 ARM_INS_VQDMLSL = 340, 793 ARM_INS_VQDMULH = 341, 794 ARM_INS_VQDMULL = 342, 795 ARM_INS_VQMOVUN = 343, 796 ARM_INS_VQMOVN = 344, 797 ARM_INS_VQNEG = 345, 798 ARM_INS_VQRDMULH = 346, 799 ARM_INS_VQRSHL = 347, 800 ARM_INS_VQRSHRN = 348, 801 ARM_INS_VQRSHRUN = 349, 802 ARM_INS_VQSHL = 350, 803 ARM_INS_VQSHLU = 351, 804 ARM_INS_VQSHRN = 352, 805 ARM_INS_VQSHRUN = 353, 806 ARM_INS_VQSUB = 354, 807 ARM_INS_VRADDHN = 355, 808 ARM_INS_VRECPE = 356, 809 ARM_INS_VRECPS = 357, 810 ARM_INS_VREV16 = 358, 811 ARM_INS_VREV32 = 359, 812 ARM_INS_VREV64 = 360, 813 ARM_INS_VRHADD = 361, 814 ARM_INS_VRINTA = 362, 815 ARM_INS_VRINTM = 363, 816 ARM_INS_VRINTN = 364, 817 ARM_INS_VRINTP = 365, 818 ARM_INS_VRINTR = 366, 819 ARM_INS_VRINTX = 367, 820 ARM_INS_VRINTZ = 368, 821 ARM_INS_VRSHL = 369, 822 ARM_INS_VRSHRN = 370, 823 ARM_INS_VRSHR = 371, 824 ARM_INS_VRSQRTE = 372, 825 ARM_INS_VRSQRTS = 373, 826 ARM_INS_VRSRA = 374, 827 ARM_INS_VRSUBHN = 375, 828 ARM_INS_VSELEQ = 376, 829 ARM_INS_VSELGE = 377, 830 ARM_INS_VSELGT = 378, 831 ARM_INS_VSELVS = 379, 832 ARM_INS_VSHLL = 380, 833 ARM_INS_VSHL = 381, 834 ARM_INS_VSHRN = 382, 835 ARM_INS_VSHR = 383, 836 ARM_INS_VSLI = 384, 837 ARM_INS_VSQRT = 385, 838 ARM_INS_VSRA = 386, 839 ARM_INS_VSRI = 387, 840 ARM_INS_VST1 = 388, 841 ARM_INS_VST2 = 389, 842 ARM_INS_VST3 = 390, 843 ARM_INS_VST4 = 391, 844 ARM_INS_VSTMDB = 392, 845 ARM_INS_VSTMIA = 393, 846 ARM_INS_VSTR = 394, 847 ARM_INS_VSUB = 395, 848 ARM_INS_VSUBHN = 396, 849 ARM_INS_VSUBL = 397, 850 ARM_INS_VSUBW = 398, 851 ARM_INS_VSWP = 399, 852 ARM_INS_VTBL = 400, 853 ARM_INS_VTBX = 401, 854 ARM_INS_VCVTR = 402, 855 ARM_INS_VTRN = 403, 856 ARM_INS_VTST = 404, 857 ARM_INS_VUZP = 405, 858 ARM_INS_VZIP = 406, 859 ARM_INS_ADDW = 407, 860 ARM_INS_ASR = 408, 861 ARM_INS_DCPS1 = 409, 862 ARM_INS_DCPS2 = 410, 863 ARM_INS_DCPS3 = 411, 864 ARM_INS_IT = 412, 865 ARM_INS_LSL = 413, 866 ARM_INS_LSR = 414, 867 ARM_INS_ORN = 415, 868 ARM_INS_ROR = 416, 869 ARM_INS_RRX = 417, 870 ARM_INS_SUBW = 418, 871 ARM_INS_TBB = 419, 872 ARM_INS_TBH = 420, 873 ARM_INS_CBNZ = 421, 874 ARM_INS_CBZ = 422, 875 ARM_INS_POP = 423, 876 ARM_INS_PUSH = 424, 877 878 // special instructions 879 ARM_INS_NOP = 425, 880 ARM_INS_YIELD = 426, 881 ARM_INS_WFE = 427, 882 ARM_INS_WFI = 428, 883 ARM_INS_SEV = 429, 884 ARM_INS_SEVL = 430, 885 ARM_INS_VPUSH = 431, 886 ARM_INS_VPOP = 432, 887 888 ARM_INS_ENDING = 433 // <-- mark the end of the list of instructions 889 } 890 891 /// Group of ARM instructions 892 enum arm_insn_group 893 { 894 ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID 895 896 // Generic groups 897 // all jump instructions (conditional+direct+indirect jumps) 898 ARM_GRP_JUMP = 1, ///< = CS_GRP_JUMP 899 ARM_GRP_CALL = 2, ///< = CS_GRP_CALL 900 ARM_GRP_INT = 4, ///< = CS_GRP_INT 901 ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE 902 ARM_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE 903 904 // Architecture-specific groups 905 ARM_GRP_CRYPTO = 128, 906 ARM_GRP_DATABARRIER = 129, 907 ARM_GRP_DIVIDE = 130, 908 ARM_GRP_FPARMV8 = 131, 909 ARM_GRP_MULTPRO = 132, 910 ARM_GRP_NEON = 133, 911 ARM_GRP_T2EXTRACTPACK = 134, 912 ARM_GRP_THUMB2DSP = 135, 913 ARM_GRP_TRUSTZONE = 136, 914 ARM_GRP_V4T = 137, 915 ARM_GRP_V5T = 138, 916 ARM_GRP_V5TE = 139, 917 ARM_GRP_V6 = 140, 918 ARM_GRP_V6T2 = 141, 919 ARM_GRP_V7 = 142, 920 ARM_GRP_V8 = 143, 921 ARM_GRP_VFP2 = 144, 922 ARM_GRP_VFP3 = 145, 923 ARM_GRP_VFP4 = 146, 924 ARM_GRP_ARM = 147, 925 ARM_GRP_MCLASS = 148, 926 ARM_GRP_NOTMCLASS = 149, 927 ARM_GRP_THUMB = 150, 928 ARM_GRP_THUMB1ONLY = 151, 929 ARM_GRP_THUMB2 = 152, 930 ARM_GRP_PREV8 = 153, 931 ARM_GRP_FPVMLX = 154, 932 ARM_GRP_MULOPS = 155, 933 ARM_GRP_CRC = 156, 934 ARM_GRP_DPVFP = 157, 935 ARM_GRP_V6M = 158, 936 ARM_GRP_VIRTUALIZATION = 159, 937 938 ARM_GRP_ENDING = 160 939 }