Address size, which can be overridden with above prefix[5].
AVX Code Condition
AVX static rounding mode
AVX Suppress all Exception
Displacement value, valid if encoding.disp_offset != 0
< encoding information
ModR/M byte
Number of operands of this instruction, or 0 when instruction has no operand.
Instruction opcode, which can be from 1 to 4 bytes in size. This contains VEX opcode as well. An trailing opcode byte gets value 0 when irrelevant.
< operands for this instruction.
Instruction prefix, which can be up to 4 bytes. A prefix byte gets value 0 when irrelevant. prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) prefix[1] indicates segment override (irrelevant for x86_64): See X86_PREFIX_CS/SS/DS/ES/FS/GS above. prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
REX prefix: only a non-zero value is relevant for x86_64
SIB value, or 0 when irrelevant.
SIB base register, or X86_REG_INVALID when irrelevant.
SIB index register, or X86_REG_INVALID when irrelevant.
SIB scale, only applicable if sib_index is valid.
SSE Code Condition
XOP Code Condition
Instruction structure